ISL6755 Datasheet, PDF (16/17 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller with Average Current Limit

ISL6755
VIN+
UL
I_P
LL
UR
L_L
LR
D1
I_S
D2
VOUT+
RTN
VIN-
FIGURE 19. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
The first power transfer period commences when switch LR
closes and the cycle repeats. The ZVS transition requires
that the leakage inductance has sufficient energy stored to
fully charge the parasitic capacitances. Since the energy
stored is proportional to the square of the current (1/2 L_LI_P2),
the ZVS resonant transition is load dependent. If the leakage
inductance is not able to store sufficient energy for ZVS, a
discrete inductor may be added in series with the
transformer primary.
Fault Conditions
A fault condition occurs if VREF or VDD fall below their
undervoltage lockout (UVLO) thresholds or if the thermal
protection is triggered. When a fault is detected, the soft-
start capacitor is quickly discharged, and the outputs are
disabled low. When the fault condition clears and the soft-
start voltage is below the reset threshold, a soft-start cycle
begins.
An overcurrent condition is not considered a fault and does
not result in a shutdown.
Thermal Protection
Internal die over-temperature protection is provided. An
integrated temperature sensor protects the device should
the junction temperature exceed +140°C. There is
approximately +15°C of hysteresis.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. V_DD and
V_REF should be bypassed directly to GND with good high
frequency capacitance.
References
[1] Ridley, R., “A New Continuous-Time Model for Current
Mode Control”, IEEE Transactions on Power
Electronics, Vol. 6, No. 2, April 1991.
16
FN6442.1
September 29, 2008