ISL6755 Datasheet, PDF(14/17 Page) Intersil Corporation – ZVS Full-Bridge PWM Controller with Average Current Limit

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

ISL6755 Datasheet, PDF (14/17 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller with Average Current Limit

◁

ISL6755

and Equation 24 becomes:

-(--2----D------â----V----e-----+-----Î----V----C----S----)----â---R----6--

Ve â ÎVCS

Î©

(EQ. 27)

The buffer transistor used to create the external ramp from

CT should have a sufficiently high gain so as to minimize the

required base current. Whatever base current is required

reduces the charging current into CT and will reduce the

oscillator frequency.

ZVS Full-Bridge Operation

The ISL6755 is a full-bridge zero-voltage switching (ZVS)

PWM controller that behaves much like a traditional

hard-switched topology controller. Rather than drive the

diagonal bridge switches simultaneously, the upper switches

(OUTUL, OUTUR) are driven at a fixed 50% duty cycle and

the lower switches (OUTLL, OUTLR) are pulse width

modulated on the trailing edge.

DEADTIME

OUTLL

OUTLR

PWM

OUTUR

RESONANT

DELAY

OUTUL

RESDEL

WINDOW

FIGURE 12. BRIDGE DRIVE SIGNAL TIMING

To understand how the ZVS method operates one must

include the parasitic elements of the circuit and examine a

full switching cycle.

VIN+

VOUT+

RTN

VIN-

FIGURE 13. IDEALIZED FULL-BRIDGE

In Figure 13, the power semiconductor switches have been

replaced by ideal switch elements with parallel diodes and

capacitance, the output rectifiers are ideal, and the

transformer leakage inductance has been included as a

discrete element. The parasitic capacitance has been

lumped together as switch capacitance, but represents all

parasitic capacitance in the circuit including winding

capacitance. Each switch is designated by its position, upper

left (UL), upper right (UR), lower left (LL), and lower right

(LR). The beginning of the cycle, shown in Figure 14, is

arbitrarily set as having switches UL and LR on and UR and

LL off. The direction of the primary and secondary currents

are indicated by IP and IS, respectively.

VIN+

VOUT+

RTN

VIN-

FIGURE 14. UL - LR POWER TRANSFER CYCLE

The UL - LR power transfer period terminates when switch

LR turns off as determined by the PWM. The current flowing

in the primary cannot be interrupted instantaneously, so it

must find an alternate path. The current flows into the

parasitic switch capacitance of LR and UR which charges

the node to VIN and then forward biases the body diode of

upper switch UR.

VIN+

VIN-

VOUT+

RTN

FIGURE 15. UL - UR FREE-WHEELING PERIOD

The primary leakage inductance, LL, maintains the current

which now circulates around the path of switch UL, the

transformer primary, and switch UR. When switch LR opens,

the output inductor current free-wheels through both output

diodes, D1 and D2. During the switch transition, the output

inductor current assists the leakage inductance in charging

the upper and lower bridge FET capacitance.

The current flow from the previous power transfer cycle

tends to be maintained during the free-wheeling period

because the transformer primary winding is essentially

shorted. Diode D1 may conduct very little or none of the

free-wheeling current, depending on circuit parasitics. This

behavior is quite different than occurs in a conventional

hard-switched full-bridge topology where the free-wheeling

current splits nearly evenly between the output diodes, and

flows not at all in the primary.

FN6442.1

September 29, 2008

▷