ISL6755 Datasheet, PDF (15/17 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller with Average Current Limit

ISL6755
This condition persists through the remainder of the
half-cycle.
During the period when CT discharges, also referred to as
the deadtime, the upper switches toggle. Switch UL turns off
and switch UR turns on. The actual timing of the upper
switch toggle is dependent on RESDEL which sets the
resonant delay. The voltage applied to RESDEL determines
how far in advance the toggle occurs prior to a lower switch
turning on. The ZVS transition occurs after the upper
switches toggle and before the diagonal lower switch turns
on. The required resonant delay is 1/4 of the period of the LC
resonant frequency of the circuit formed by the leakage
inductance and the parasitic capacitance. The resonant
transition may be estimated from Equation 28.
τ
=
π_{-- -----------------}1_{------------------}
2
------¹--------
L_LC_P
–
--^R-----²--
4 L _L2
(EQ. 28)
where τ is the resonant transition time, L_L is the leakage
inductance, C_P is the parasitic capacitance, and R is the
equivalent resistance in series with L_L and C_P.
The resonant delay is always less than or equal to the
deadtime and may be calculated using Equation 29.
τ_resdel
=
-^V----^r--^e---^s---^d----^e--^l
2
⋅
D
T
S
(EQ. 29)
where τ_resdel is the desired resonant delay, V_resdel is a
voltage between 0 and 2V applied to the RESDEL pin, and
DT is the deadtime (see Equations 1 through 5).
When the upper switches toggle, the primary current that
was flowing through UL must find an alternate path. It
charges/discharges the parasitic capacitance of switches UL
and LL until the body diode of LL is forward biased. If
RESDEL is set properly, switch LL will be turned on at this
time.The output inductor does not assist this transition. It is
purely a resonant transition driven by the leakage
inductance.
VIN+
UL
I_P
LL
UR
L_L
LR
D1
I_S
D2
VOUT+
RTN
VIN-
FIGURE 16. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
The second power transfer period commences when switch
LL closes. With switches UR and LL on, the primary and
secondary currents flow as indicated in Figure 17.
VIN+
UL
UR
D1
L_L
VOUT+
RTN
LL
LR
D2
VIN-
FIGURE 17. UR - LL POWER TRANSFER
The UR - LL power transfer period terminates when switch
LL turns off as determined by the PWM. The current flowing
in the primary must find an alternate path. The current flows
into the parasitic switch capacitance which charges the node
to V_IN and then forward biases the body diode of upper
switch UL. As before, the output inductor current assists in
this transition. The primary leakage inductance, L_L,
maintains the current, which now circulates around the path
of switch UR, the transformer primary, and switch UL. When
switch LL opens, the output inductor current free-wheels
predominantly through diode D1. Diode D2 may actually
conduct very little or none of the free-wheeling current,
depending on circuit parasitics. This condition persists
through the remainder of the half-cycle.
VIN+
UL
I_P
UR
L_L
D1
I_S
LL
LR
D2
VIN-
FIGURE 18. UR - UL FREE-WHEELING PERIOD
VOUT+
RTN
When the upper switches toggle, the primary current that
was flowing through UR must find an alternate path. It
charges/discharges the parasitic capacitance of switches UR
and LR until the body diode of LR is forward biased. If
RESDEL is set properly, switch LR will be turned on at this
time.
15
FN6442.1
September 29, 2008