ISL65426_07 Datasheet, PDF (16/22 Pages) Intersil Corporation – 6A Dual Synchronous Buck Regulator with Integrated MOSFETs

ISL65426
in Table 2. When Each pin is pulled to GND by an internal
10μA pull down, this default condition programs the output
voltage to the lowest level. The pull down prevents situations
where a pin could be left floating for example (cold solder
joint) from causing the output voltage to rise above the
programmed level and damage a sensitive load device.
TABLE 2. OUTPUT VOLTAGE PROGRAMMING
VOUT1 V1SET1 V1SET2 VOUT2 V2SET1 V2SET2
1.8V
1
1
3.3V
1
1
1.5V
0
1
2.5V
0
1
1.2V
1
0
1.8V
1
0
0.6V
0
0
0.6V
0
0
ISL65426
EXTERNAL CONDITIONS
L_OUT
LX
C_OUT
V_OUT
1.4V
R1
13.3kΩ
FB
R2
10kΩ
FIGURE 36. EXTERNAL OUTPUT VOLTAGE SELECTION
For designers requiring an output voltage level outside those
shown Table 2, the ISL65426 allows user programming with
an external resistor divider (see Figure 4). First, both
channel selection pins associated with that output channel
must tied to GND to set the internal reference to 0.6V. Next,
the output voltage is set by an external resistive divider
according to Equation 1. R2 is selected arbitrarily, but 5kΩ or
10kΩ is usually a good starting point. The designer can
configure the output voltage from 1V to 4V from a 5V power
supply. Lower input supply voltages reduce the maximum
programmable output voltage to 80% of the input voltage
level.
R1
=
R
2
⋅
-^V----^O----^U----^T-----–-----⁰---^.--⁶---^V---
0.6 V
(EQ. 1)
Switching Frequency
The controller features an internal oscillator running at a
fixed frequency of 1MHz. The oscillator tolerance is +10%
over input bias and load range.
Operation Initialization
The ISL65426 initializes based on the state of three enable
inputs (EN, EN1, EN2) and power-on reset (POR) monitors
on VCC and PVINx inputs. Successful initialization of the
controller prompts a one time power block configuration
check. Verification of proper phase connections lead to a
soft-start interval. The controller begins slowly ramping the
output voltages based on the enable input states. Once the
commanded output voltage is within the proper window of
operation, the power good signal corresponding to the active
channel changes state from low to high indicating proper
operation initialization.
Power-On Reset
The POR circuitry prevents the controller from attempting to
soft-start before sufficient bias is present at vital power
supply input pins. These include the VCC and PVINx pins.
The VCC pins have a variable POR threshold based on the
output voltage configuration pin configuration of VOUT2. If
the configuration pins are set for 2.5V, the VCC POR rising
threshold is typically 2.9V. The 3.3V configuration increases
the VCC POR level to 4.3V. This variable rising threshold
guarantees that the controller can properly switch the
internal power blocks at the assigned output voltage levels.
The PVINx pins have a set POR rising threshold for all
output voltage configurations. While the voltage on these
pins are below this threshold, as defined in the “Electrical
Specifications” table on page 7, the controller inhibits
switching of the internal power MOSFETs.
Built-in hysteresis between the rising and falling thresholds
insures that once enabled, the controller will not
inadvertently toggle turn off unless the bias voltage drops
substantially. While these pins are below the POR rising
threshold, the synchronous power switch LX pins are held in
a high-impedance state.
If additional POR control is required, a system enable input
can be used to govern initialization as described in the next
section.
Enable and Disable
If the POR input requirements are met, the ISL65426
remains in shutdown until the voltage at the enable inputs
rise above their enable thresholds. Independent enable
inputs, EN1 and EN2, allow initialization of either buck
converter channel separately, sequenced, or simultaneously.
Both pins feature a 10mA pull-up which will initialize both
sides once the voltage at their respective pins exceeds the
rising enable threshold, as defined in the “Electrical
Specifications” table on page 7.
Both converters are governed by the presence of a system
enable, EN (See Figure 5). When two separate input
supplies are used for each channel of power blocks or an
external signal needs to govern the power-up sequence, the
system enable provides a startup sequencing mechanism.
The system enable features an internal 10mA pull-down
which is only active when the voltage on the EN pin is below
the enable threshold. The current sink pulls the EN pin low.
As VCC2 rises the enable level is not set exclusively by the
resistor divider from VCC2. With the current sink active, the
enable level is defined in Equation 2. R1 is the resistor EN to
VCC2 and R2 is the resistor from EN to GND.
16
FN6340.2
February 21, 2007