ISL65426_07 Datasheet, PDF (15/22 Pages) Intersil Corporation – 6A Dual Synchronous Buck Regulator with Integrated MOSFETs

ISL65426
EN
System enable for voltage monitoring with programmable
hysteresis. This pin has a POR rising threshold of 0.6V. This
enable is intended for applications where two or more input
power supplies are used and bias rise time is an issue.
EN1, EN2
These pins are threshold-sensitive enable inputs for the
individual PWM converters. These pins have low current
(10μA) internal pull-ups to VCC. This pin disables the
respective converter until pulled above a 1V rising threshold.
ISET1, ISET2
Power block configuration inputs. Select the proper state for
each pin according to Table 1.
V1SET1, V1SET2, V2SET1, V2SET2
Output voltage configuration inputs. Select the proper state
of each pin per the electrical specification table.
PG1, PG2
Power good output. Open drain logic output that is pulled to
ground when the output voltage is outside regulation limits.
Functional Description
The ISL65426 is a monolithic, constant frequency, current-
mode dual output buck converter controller with user
configurable power blocks. Designed to provide a total
DC/DC solution for FPGAs, CPLDs, core processors, and
ASICs.
PVIN1
LX1
PVIN2
LX2
PVIN3
LX3
POWER BLOCK 1 POWER BLOCK 6
PVIN6
LX6
POWER BLOCK 2 _{POWER BLOCK 5}
PVIN5
LX5
POWER BLOCK 3 POWER BLOCK 4
PVIN4
LX4
MASTER POWER BLOCK
FLOATING POWER BLOCK
FIGURE 35. POWER BLOCK DIAGRAM
Power Blocks
A unique power block architecture allows partitioning of six
1A capable modules to support one of four power block
configuration options. The block diagram in Figure 3
provides a top level view of the power block layout. One
master power block is assigned to each converter output
channel. Power Block 2 is allotted to converter Channel 1
and Power Block 5 to Channel 2. The master power blocks
must not be tied together or the controller will not soft-start.
The remaining four floating power blocks can be partitioned
in one of four valid states outlined in Table 1. The controller
detects the programmed configuration based on the state of
logic signals at pins ISET1 and ISET2. The controller checks
the power block configuration versus the programmed
configuration before the either converter can soft-start.
Each power block has a separate power supply connection
pin, PVINx, and common channels must join these inputs to
one input power supply. Common synchronous power switch
connection points for each channel must be tied together
and to an external inductor. See the “Typical Application
Schematics” for pin connection guidance.
TABLE 1. POWER BLOCK CONFIGURATION
I1SET I2SET I_OUT1
1
1
3A
CHANNEL 1
CONNECTIONS I_OUT2
LX1,LX2,LX3 3A
CHANNEL 2
CONNECTIONS
LX4,LX5,LX6
1
0
4A LX1,LX2,LX3,LX4 2A
LX5,LX6
0
1
5A LX1,LX2,LX3,LX4 1A
LX5
,LX6
0
0
2A
LX1,LX2
4A LX3,LX4,LX5,LX6
Invalid LX Configurations: SS Prevented
X
X
1A
LX2
5A
LX1,LX3,LX4,
LX5,LX6
Each power block has a scaled pilot device providing current
feedback. The configuration pin settling determines how the
controller handles separation and summing of the individual
current feedback signals.
Main Control Loop
The ISL65426 is a monolithic, constant frequency, current-
mode step-down DC/DC converter. During normal operation,
the internal top power switch is turned on at the beginning of
each clock cycle. Current in the output inductor ramps up
until the current comparator trips and turns off the top power
MOSFET. The bottom power MOSFET turns on and the
inductor current ramps down for the rest of the cycle.
The current comparator compares the output current at the
ripple current peak to a current pilot. The error amplifier
monitors V_OUT and compares it with the internal voltage
reference. The error amplifier’s output voltage drives a
proportional current to the pilot. If V_OUT is low the pilot’s
current level is increased and the trip off current level of the
output is increased. The increased current works to raise the
V_OUT level into agreement with the voltage reference.
Output Voltage Programming
The feedback voltage applied to the inverting input of the
error amplifier is scaled internally relative to the 0.6V internal
reference voltage based on the state of logic signals at pins
V1SET1, V1SET2, V2SET1 and V2SET2. The output
voltage configuration logic decodes the 2-bit voltage
identification codes into one of the discrete voltages shown
15
FN6340.2
February 21, 2007