ISL6446A Datasheet, PDF (16/20 Pages) Intersil Corporation – Dual (180°Out-of-Phase) PWM and Linear Controller

ISL6446A
Feedback Compensation Equations
This section highlights the design consideration for a voltage
mode controller requiring external compensation. To address a
broad range of applications, a type-3 feedback network is
recommended (see Figure 25).
C2
R2 ^C1
COMP
FB
C3
R1
R3
ISL6446A
V_OUT
FIGURE 25. COMPENSATION CONFIGURATION FOR ISL6446A CIRCUIT
Figure 26 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable to the ISL6446A
circuit. The output voltage (V_OUT) is regulated to the reference
voltage, V_REF. The error amplifier output (COMP pin voltage) is
compared with the oscillator (OSC) modified sawtooth wave to
provide a pulse-width modulated wave with an amplitude of V_IN
at the PHASE node. The PWM wave is smoothed by the output
filter (L and C). The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor E.
The modulator transfer function is the small-signal transfer
function of V_OUT/V_COMP. This function is dominated by a DC gain,
given by d_MAXV_IN/V_OSC, and shaped by the output filter, with a
double pole break frequency at F_LC and a zero at F_CE. For the
purpose of this analysis, L and D represent the channel
inductance and its DCR, while C and E represent the total output
capacitance and its equivalent series resistance.
C2
COMP
R2 _C1
-
FB
E/A ⁺
VREF
R3 ^C3
R1
Ro
PWM
CIRCUIT
OSCILLATOR
V_OSC
HALF-BRIDGE
DRIVE
V_IN
L
UGATE
PHASE
LGATE
V_OUT
D
C
E
ISL6446A EXTERNAL CIRCUIT
FIGURE 26. VOLTAGE-MODE BUCK CONVERTER COMPENSATION
DESIGN
F_LC=
-------------¹--------------
2π ⋅ L ⋅ C
(EQ. 11)
F_CE= ₂----_π-----_â‹--¹-_C------_â‹---_E--
(EQ. 12)
The compensation network consists of the error amplifier
(internal to the ISL6446A) and the external R1 to R3, C1 to C3
components. The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing frequency
(F₀; typically 0.1 to 0.3 of F_SW) and adequate phase margin
(better than 45°). Phase margin is the difference between the
closed loop phase at F_0dB and 180°. The equations that follow
relate the compensation network’s poles, zeros and gain to the
components (R1 , R2, R3, C1 , C2, and C3) in Figure 26. Use the
following guidelines for locating the poles and zeros of the
compensation network:
1. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate the
value for R2 for desired converter bandwidth (F₀). If setting
the output voltage via an offset resistor connected to the FB
pin, Ro in Figure 26, the design procedure can be followed as
presented in Equation 13.
R2
=
---^V----^O-----^S----^C-----^â‹---^R-----¹-----^â‹---^F----⁰----
d_MAX ⋅ V_IN ⋅ F_LC
(EQ. 13)
16
FN8384.1
November 6, 2012