ISL6446A Datasheet, PDF (12/20 Pages) Intersil Corporation – Dual (180°Out-of-Phase) PWM and Linear Controller

ISL6446A
Functional Description
Soft-Start and Voltage Tracking
After the VCC pin exceeds its rising POR trip point (nominal 4.4V),
the chip operation begins. Both 30µA current sources will start
charging up the soft-starting capacitors respectively. The
charging continues until the voltage across the soft-start
capacitor reaches about 3.2V. From 1.0V to 1.6V, the outputs will
ramp individually from zero to full-scale. Now, if V = 0.6V,
C = 0.1µF, and I = 30µA, then t = 2ms. Figure 18 shows the
typical waveforms for SS2/EN2 and V_OUT2; SS1/EN1 and V_OUT1
are similar.
SS2/EN2 (0.5V/DIV)
1.6V
1.0V
V_OUT2 (2V/DIV)
GND>
FIGURE 18. SOFT-START
The soft-start ramps for each output can be selected
independently.
The basic timing equation is shown in Equation 2:
t
=
C
•
d_----V_---
I
(EQ. 2)
where:
t is the charge time
C is the external capacitance
dV is the voltage charged
I is the charging current (nominal 30µA)
Finally, there is a delay after 1.6V, until the ramp gets to ~3.2V,
which signals that the ramp is done; when both ramps are done,
the PGOOD delay begins. To guarantee the soft-start is
completed, please make sure the EN/SSx pin voltage is able to
reach above 3.2V at normal operation.
V_OUT2 (1V/DIV)
GND>
1.6V
1.0V
SS1/EN1 (0.5V/DIV)
V_OUT (1V/DIV)
SS2/EN2 (0.5V/DIV)
GND>
FIGURE 19. VOLTAGE TRACKING
Figure 20 shows pre-biased outputs before soft-start. The solid
blue curve shows no pre-bias; the output starts ramping from
GND. The magenta dotted line shows the output pre-biased to a
voltage less than the final output. The FETs don’t turn on until the
soft-start ramp voltage exceeds the output voltage; then the
output starts ramping seamlessly from there. The cyan dotted
line shows the output pre-biased above the final output (but
below the OVP (Overvoltage Protection)). The FETs will not turn on
until the end of the soft-start ramp; then the output will be
quickly pulled down to the final value.
If the output is pre-biased above the OVP level, the ISL6446A will
go into OVP at the end of soft-start, which will keep the FETs off.
See “Protection Mechanisms” on page 14 for more details.
VOUT1 has the same functionality as previously described for
VOUT2. Each output should react independently of the other,
unless they are related by the circuit configuration.
SS2/EN2 (0.5V/DIV)
V_OUT2 OVER-CHARGED
V_OUT2 PRE-BIASED
GND>
V_OUT2 (2V/DIV)
FIGURE 20. SOFT-START WITH PRE-BIAS
The linear output does not have a soft-start ramp; however, it
may follow the ramp of its input supply, if timed to coincide with
its rise, after the VCC rising POR trip. If the input to the linear is
from one of the two switcher outputs, then it will share the same
ramp rate as the switcher.
12
FN8384.1
November 6, 2012