ISL6446A Datasheet, PDF (13/20 Pages) Intersil Corporation – Dual (180°Out-of-Phase) PWM and Linear Controller

ISL6446A
PGOOD
A group of comparators (separate from the protection
comparators) monitor the output voltages (via the FB pins) for
PGOOD. Each switcher has a lower and upper boundary
(nominally around 90% and 110% of the target value) and the
linear has a lower boundary (around 75% of the target). Once
both switcher output ramps are done, and all 3 outputs are
within their expected ranges, the PGOOD will start an internal
timer, with Equation 3:
t_PGOOD
=
0_----._-0_----6_---5_--
F_SW
(EQ. 3)
where:
t_PGOOD is the delay time (in sec)
F_SW is the switching frequency (in MHz)
Once the time-out is complete, the internal pull-down device will
shut off, allowing the open-drain PGOOD output to rise through an
external pull-up resistor, to a 5V (or lower) supply, which signals
that the “Power is GOOD”. Figure 21 shows the three outputs
turning on, and the delay for PGOOD. If any of the conditions is
subsequently violated, then PGOOD goes low. Once the voltage
returns to the normal region, a new delay will start, after which the
PGOOD will go high again.
The PGOOD delay is inversely proportional to the clock frequency.
If the clock is running as slow as 524kHz, the delay will be
125ms long. There is no way to adjust the PGOOD delay
independently of the clock.
GND>
PGOOD (5V/DIV)
GND>
GND>
V_OUT3 (2V/DIV)
V_OUT2 (2V/DIV)
GND>
V_OUT1 (2V/DIV)
FIGURE 21. PGOOD DELAY
Switching Frequency
The switching frequency of the ISL6446A is determined by the
external resistor placed from the RT pin to SGND. See Figure 22
for a graph of Frequency vs RT Resistance. Use Equation 4 to
calculate the approximate RT resistor value for the desired
switching frequency. The typical resistance for 100kHz operation
is 163kΩ. Running at both high frequency and high V_IN voltages
is not recommended, due to the increased power dissipation
on-chip (mostly from the internal VCC regulator, which supplies
gate drivers). The user should check the maximum acceptable IC
temperature, based on their particular conditions.
R_T
=
⎛
⎝
1^--F--1^--S-2^---W-9^---0^{--⎠⎞}
–1.093
(EQ. 4)
300k
100k
50k
30k
10k
3k
100k
200k
500k
1M
2M
SWITCHING FREQUENCY (Hz)
FIGURE 22. FREQUENCY vs R_T RESISTOR
Output Regulation
Figure 23 shows the generic feedback resistor circuit for any of
the two PWM V_OUT’s; the V_OUT is divided down to equal the
reference. All three use a 0.6V internal reference (check the
“Electrical Specifications” Table on page 6 for the exact reference
value at 24V). The R_UP is connected to the V_OUT; the R_LOW to
GND; the common point goes to the FB pin.
V_OUT
R_UP
FB
COMP
EA
R_LOW
0.6V
FIGURE 23. OUTPUT REGULATION
V_OUT must be greater than 0.6V and 2 resistors are needed, and
their accuracy directly affect the regulator tolerance.
FB
=
V_OUT
⋅
----------^R----^L----^O----^W-------------
R_UP + R_LOW
(EQ. 5)
Use Equation 6 to choose the resistor values. R_UP is part of the
compensation network for the switchers, and should be selected
to be compatible; 1kΩ to 5kΩ is a good starting value. Find FB
from the “Electrical Specifications” Table on page 7 (for the right
condition), plug in the desired value for V_OUT, and solve for R_LOW.
R_LOW
=
---^F----^B------^â‹---^R----^U-----^P----
V_OUT – FB
(EQ. 6)
The maximum duty cycle of the ISL6446A approaches 100% at
low frequency, but falls off at higher frequency; see the
“Electrical Specifications” Table on page 7. In addition, there is a
minimum UGATE pulse width, in order to properly sense
overcurrent. The two switchers are 180° out of phase.
13
FN8384.1
November 6, 2012