ISL6314CRZ-T Datasheet, PDF (16/32 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications

ISL6314
The output of the error amplifier, V_COMP, is compared to the
sawtooth waveform to generate the PWM signal. The PWM
signal controls the timing of the Internal MOSFET drivers
and regulates the converter output so that the voltage at FB
is equal to the voltage at REF. This will regulate the output
voltage to be equal to Equation 4. The internal and external
circuitry that controls voltage regulation is illustrated in
Figure 4.
EXTERNAL CIRCUIT
R_C C_{C COMP}
ISL6314 INTERNAL CIRCUIT
R_FB
+
V_OFS
-
REF
C_REF
FB
VDIFF
VID DAC
2k
+
-
V_COMP
ERROR AMPLIFIER
I_OFS
VSEN
+
+
V_OUT
+
-
RGND
+
V_DROOP
-
ISEN+
ISENO
-
-
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 4. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
Load-Line (Droop) Regulation
Some microprocessor manufacturers require a
precisely-controlled output resistance. This dependence of
output voltage on load current is often termed “droop” or
“load line” regulation. By adding a well controlled output
impedance, the output voltage can effectively be level shifted
in a direction which works to achieve the load-line regulation
required by these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
.
PHASE
ISEN-
V_L(s)
L
DCR
INDUCTOR
IL
R_S
I_OUT
V_OUT
C_OUT
ISENO
-
V_DROOP
+ ^ISEN+
C_COMP R_COMP
(OPTIONAL)
ISL6314
FIGURE 5. DCR SENSING CONFIGURATION
As shown in Figure 5, a voltage, V_DROOP, proportional to the
current in the channel, I_OUT, feeds into the differential
remote-sense amplifier. The resulting voltage at the output of
the remote-sense amplifier is the sum of the output voltage
and the droop voltage. Equation 5 shows that feeding this
voltage into the compensation network causes the regulator
to adjust the output voltage so that it’s equal to the reference
voltage minus the droop voltage.
The droop voltage, V_DROOP, is created by sensing the
current through the output inductors. This is accomplished
by using a continuous DCR current sensing method.
Inductor windings have a characteristic distributed
resistance or DCR (Direct Current Resistance). For
simplicity, the inductor DCR is considered as a separate
lumped quantity, as shown in Figure 5. The channel current,
I_L, flowing through the inductor, passes through the DCR.
Equation 5 shows the S-domain equivalent voltage, V_L,
across the inductor.
V_L(s) = I_L ⋅ (s ⋅ L + DCR)
(EQ. 5)
The inductor DCR is important because the voltage dropped
across it is proportional to the channel current. By using a
simple R-C network and a current sense amplifier, as shown
in Figure 5, the voltage drop across the inductor’s DCR can
be extracted. The output of the current sense amplifier,
V_DROOP, can be shown to be proportional to the channel
current I_L, shown in Equation 6.
VDROOP(s)
=
⎛
⎝
--^s-----^â‹---^L---
DCR
+
1_⎠⎞
-------------------------------------------------------------------------
(s ⋅ RCOMP ⋅ CCOMP + 1)
⋅
R_{-----C-----O-----M-----P---}
RS
⋅ (IL) ⋅ DCR
(EQ. 6)
If the R-C network components are selected such that the
R-C time constant matches the inductor L/DCR time
constant, then V_DROOP is equal to the voltage drop across
the DCR, multiplied by a gain. As Equation 7 shows,
V_DROOP is therefore proportional to the total output current,
I_OUT.
16
FN6455.2
October 8, 2009