ISL6314CRZ-T Datasheet, PDF (11/32 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications

ISL6314
EXTERNAL CIRCUIT
APA
ISL6314 INTERNAL CIRCUIT
C_APA
R_{APA VAPA,TRIP}
COMP
100µA
LOW
PASS
FILTER
+
APA
-
TO APA
CIRCUITRY
ERROR
AMPLIFIER
FIGURE 2. ADAPTIVE PHASE ALIGNMENT DETECTION
As Figure 2 shows, the APA circuitry works by monitoring the
voltage on the APA pin and comparing it to a filtered copy of
the voltage on the COMP pin. The voltage on the APA pin is
a copy of the COMP pin voltage that has been negatively
offset. If the APA pin exceeds the filtered COMP pin voltage
an APA event occurs and the channel is forced on.
The APA trip level is the amount of DC offset between the
COMP pin and the APA pin. This is the voltage excursion
that the APA and COMP pin must have during a transient
event to activate the Adaptive Phase Alignment circuitry.
This APA trip level is set through a resistor, R_APA, that
connects from the APA pin to the COMP pin. A 100µA
current flows across R_APA into the APA pin to set the APA
trip level as described in Equation 3. An APA trip level of
500mV is recommended for most applications. A 1000pF
capacitor, C_APA, should also be placed across the R_APA
resistor to help with noise immunity.
V_{APA, TRIP} = R_APA ⋅ 100 × 10^–6
(EQ. 3)
Active Pulse Positioning (APP) Modulated PWM
Operation
The ISL6314 uses a proprietary Active Pulse Positioning
(APP) modulation scheme to control the internal PWM
signals that command each channel’s driver to turn their
upper and lower MOSFETs on and off. The time interval in
which a PWM signal can occur is generated by an internal
clock, whose cycle time is the inverse of the switching
frequency set by the resistor connected to the FS pin. The
advantage of Intersil’s proprietary Active Pulse Positioning
(APP) modulator is that the PWM signal has the ability to
turn on at any point during this PWM time interval, and turn
off immediately after the PWM signal has transitioned high.
This is important because is allows the controller to quickly
respond to output voltage drops associated with current load
spikes, while avoiding the ring back affects associated with
other modulation schemes.
The PWM output state is driven by the position of the error
amplifier output signal, V_COMP, as illustrated in Figure 3. At
the beginning of each PWM time interval, this V_COMP signal
is compared to the internal modulator waveform. As long as
the V_COMP voltage is lower then the modulator waveform
voltage, the PWM signal is commanded low. The internal
MOSFET driver detects the low state of the PWM signal and
turns off the upper MOSFET and turns on the lower
synchronous MOSFET. When the V_COMP voltage crosses
the modulator ramp, the PWM output transitions high,
turning off the synchronous MOSFET and turning on the
upper MOSFET. The PWM signal will remain high until the
V_COMP voltage crosses the modulator ramp again. When
this occurs, the PWM signal will transition low again.
During each PWM time interval, the PWM signal can only
transition high once. Once PWM transitions high, it can not
transition high again until the beginning of the next PWM
time interval. This prevents the occurrence of double PWM
pulses occurring during a single period.
V_COMP
MODULATOR
RAMP
WAVEFORM
PWM
+
-
TO GATE
CONTROL
LOGIC
FIGURE 3. CHANNEL PWM FUNCTION
Output Voltage Setting
The ISL6314 uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at
the VID pins. The DAC decodes the logic signals into one of
the discrete voltages shown in Tables 2, 3 or 4. In the Intel
VR11 mode of operation, each VID pin is pulled up to an
internal 1.2V voltage by a weak current source (40µA),
which decreases to 0A as the voltage at the VID pin varies
from 0 to the internal 1.2V pull-up voltage. In AMD modes of
operation, the VID pins are pulled low by a weak 20µA
current source. External pull-up resistors or active-high
output stages can augment the pull-up current sources, up to
a voltage of 5V.
._{The ISL6314 accommodates three different DAC ranges:}
Intel VR11, AMD K8/K9 5-bit, and AMD 6-bit. The state of
the SS and VID7 pins decide which DAC version is active.
Refer to Table 1 for a description of how to select the desired
DAC version.
11
FN6455.2
October 8, 2009