ISL78208 Datasheet, PDF (15/25 Pages) Intersil Corporation – Wide VIN Dual Standard Buck Regulator with 3A/3A Continuous Output Current

ISL78208
Detailed Description
The ISL78208 combines a standard buck PWM controller with an
integrated switching MOSFET. The buck controller drives an
internal N-Channel MOSFET and requires an external diode to
deliver load current up to 3A. A Schottky diode is recommended
for improved efficiency and performance over a standard diode.
The standard buck regulator can operate from an unregulated DC
source, such as a battery, with a voltage ranging from +4.5V to
+28V. The converter output can be regulated to as low as 0.8V.
These features make the ISL78208 ideally suited for
infotainment system power, and DSP and embedded processor
power supply applications.
The ISL78208 employs a peak current mode control loop which
simplifies feedback loop compensation and rejects input voltage
variation. External feedback loop compensation allows flexibility
in output filter component selection. The regulator switches at a
default 500kHz and it can be adjusted from 300kHz to 2MHz
with a resistor from FS to GND. The ISL78208 is also
synchronizable from 300kHz to 2MHz.
Operation Initialization
The power-ON reset circuitry and enable inputs prevent false
start-up of the PWM regulator output. Once all input criteria are
met, the controller soft-starts the output voltage to the
programmed level.
Power-On Reset and Undervoltage Lockout
The ISL78208 automatically initializes upon receipt of input
power supply. The power-on reset (POR) function continually
monitors VIN1 voltage. While below the POR threshold, the
controller inhibits switching of the internal power MOSFET. Once
exceeded, the controller initializes the internal soft-start circuitry.
If VIN1 supply drops below their falling POR threshold during
soft-start or operation, the buck regulator is disabled until the
input voltage returns.
Enable and Disable
When EN1 and EN2 are pulled low, the device enters shutdown
mode and the supply current drops to a typical value of 20µA. All
internal power devices are held in a high-impedance state while
in shutdown mode.
The EN pin enables the controller of the ISL78208. When the
voltage on the EN pin exceeds its logic rising threshold, the
controller initiates the 2ms soft-start function for the PWM
regulator. If the voltage on the EN pin drops below the falling
threshold, the buck regulator shuts down.
If EN1, EN2 pins are driven by an external signal, the minimum
off-time for EN1, EN2 should be:
EN_T_off (μs) = 10μs • C_SS ⁄ 2.2nF
(EQ. 1)
where C_SS is the soft-start pin capacitor (nF). ISL78208 does not
have debouncing to EN1, EN2 external signals.
Power-Good
PG is the open-drain output of a window comparator that
continuously monitors the buck regulator output voltage via the FB
pin. PG is actively held low when EN is low and during the buck
regulator soft-start period. After the soft-start period terminates,
PG becomes high impedance as long as the output voltage
(monitored on the FB pin) is above 90% of the nominal regulation
voltage set by FB. When V_OUT drops 10% below the nominal
regulation voltage, the ISL78208 pulls PG low. Any fault condition
forces PG low until the fault condition is cleared by attempts to
soft-start. There is an internal 5MΩ internal pull-up resistor.
Output Voltage Selection
The regulator output voltages is easily programmed using an
external resistor divider to scale V_OUT relative to the internal
reference voltage. The scaled voltage is applied to the inverting
input of the error amplifier; refer to Figure 38.
The output voltage programming resistor, R₂, depends on the
value chosen for the feedback resistor, R₃, and the desired
output voltage, V_OUT, of the regulator. Equation 2 describes the
relationship between V_OUT and resistor values. R₃ is often
chosen to be in the 1kΩ to 10kΩ range.
R₂ = (V_OUT – 0.8 ) • R₃ ⁄ 0.8
(EQ. 2)
If the desired output voltage is 0.8V, then R₃ is left unpopulated
and R₂ is 0Ω.
R₂
FB
V_OUT
EA
R₃
0.8V
REFERENCE
FIGURE 38. EXTERNAL RESISTOR DIVIDER
Output Tracking and Sequencing
Output tracking and sequencing between channels can be
implemented by using the SS1 and SS2 pins. Figures 39, 40 and
41 show several configurations for output tracking/sequencing
for a 5.0V and 3.3V application. Independent soft-start for each
channel is shown in Figure 39 and measured in Figure 29. The
output ramp-time for each channel (t_SS) is set by the soft-start
capacitor (C_SS).
C_SS[μF] = 2.5*t_SS(s)
(EQ. 3)
Maximum C_SS value is 50nF.
Ratiometric tracking is achieved in Figure 40 by using the same
value for the soft-start capacitor on each channel; it is measured
in Figure 30.
By connecting a feedback network from V_OUT1 to the SS2 pin
with the same ratio that sets V_OUT2 voltage, absolute tracking
shown in Figure 41 is implemented. The measurement is shown
in Figure 31. If the output of Channel 1 is shorted to GND, it will
enter overcurrent hiccup mode, SS2 will be pulled low through
the added resistor between V_OUT1 and SS2 and this will force
Channel 2 into hiccup as well. If the output of Channel 2 is
shorted to GND with VOUT1 in regulation, it will enter overcurrent
15
FN8354.0
July 12, 2013