ISL6721ABZ-T Datasheet, PDF (15/22 Pages) Intersil Corporation – Flexible Single-ended Current Mode PWM Controller

ISL6721
resistance in the gate drive circuit, a portion of this power will
be dissipated externally.
Pgate = Qg • Vg • f_sw
W
(EQ. 22)
Once the losses are known, the device package must be
selected and the heatsinking method designed. Since the
design requires a small surface mount part, a 8 Ld SOIC
package was selected. A Fairchild FDS2570 MOSFET was
selected based on these criteria. The overall losses are
estimated at 400mW.
Output Filter Design
In a flyback design, the primary concern for the design of the
output filter is the capacitor ripple current stress and the
ripple and noise specification of the output.
The current flowing in and out of the output capacitors is the
difference between the winding current and the output current.
The peak secondary current, I_SPK, is 10.73A for the 3.3V
output and 4.29A for the 1.8V output. The current flowing into
the output filter capacitor is the difference between the winding
current and the output current. Looking at the 3.3V output, the
peak winding current is I_SPK = 10.73A. The capacitor must
store this amount minus the output current of 2.5A, or 8.23A.
The RMS ripple current in the 3.3V output capacitor is about
3.5A_RMS. The RMS ripple current in the 1.8V output capacitor
is about 1.4A_RMS.
Voltage deviation on the output during the switching cycle
(ripple and noise) is caused by the change in charge of the
output capacitance, the equivalent series resistance (ESR),
and equivalent series inductance (ESL). Each of these
components must be assigned a portion of the total ripple
and noise specification. How much to allow for each
contributor is dependent on the capacitor technology used.
For purposes of this discussion, we will assume the following:
3.3V output: 100mV total output ripple and noise
ESR: 60mV
Capacitor ΔQ: 10mV
ESL: 30mV
1.8V output: 50mV total output ripple and noise
ESR: 30mV
Capacitor ΔQ: 5mV
ESL: 15mV
For the 3.3V output:
ESR
≤
-------------^Δ----^V---------------
I_SPK – I_OUT
=
--------⁰---^.--⁰---⁶---⁰---------
10.73 – 2.5
=
7.3 m Ω
(EQ. 23)
The change in voltage due to the change in charge of the
output capacitor, ΔQ, determines how much capacitance is
required on the output.
C ≥ -⁽--^I--^s----^p---^k---₂--–---_•-^I--^o-_Δ---^u-_V---^t--⁾----^•----^T----^r
=
-⁽--¹---⁰----^.-⁷----³----–-----²---^.--⁵----⁾---^•----²----^.-³----³----^×---1---0---^–---⁶-
2 • 0.010
=
960 μ F
(EQ. 24)
ESL adds to the ripple and noise voltage in proportion to the
rate of change of current into the capacitor (V = L • di/dt).
L
≤
V_------•_----d_----t
di
=
0_----._-0_----3_---0_-----•_----2_----0_---0_----×_---1---0---^–_---⁹_-
10.73
=
0.56 n H
(EQ. 25)
Capacitors having high capacitance usually do not have
sufficiently low ESL. High frequency capacitors such as
surface mount ceramic or film are connected in parallel with
the high capacitance capacitors to address the effects of
ESL. A combination of high frequency and high ripple
capability capacitors is used to achieve the desired overall
performance. The analysis of the 1.8V output is similar to
that of the 3.3V output and is omitted for brevity. Two
OSCON 4SEP560M (560µF) electrolytic capacitors and a
22µF X5R ceramic 1210 capacitor were selected for both the
3.3 and 1.8V outputs. The 4SEP560M electrolytic capacitors
are each rated at 4520mA ripple current and 13mΩ of ESR.
The ripple current rating of just one of these capacitors is
adequate, but two are needed to meet the minimum ESR
and capacitance values.
The bias output is of such low power and current that it
places negligible stress on its filter capacitor. A single 0.1µF
ceramic capacitor was selected.
Control Loop Design
The major components of the feedback control loop are a
programmable shunt regulator, an opto-coupler, and the
inverting amplifier of the ISL6721. The opto-coupler is used
to transfer the error signal across the isolation barrier. The
opto-coupler offers a convenient means to cross the
isolation barrier, but it adds complexity to the feedback
control loop. It adds a pole at about 10kHz and a significant
amount of gain variation due the current transfer ratio (CTR).
The CTR of the opto-coupler varies with initial tolerance,
temperature, forward current, and age.
A block diagram of the feedback control loop is shown in
Figure 7.
PRIMARY SIDE AMPLIFIER
REF +
Z3
-
PWM
POWER
STAGE
VOUT
Z4
ERROR AMPLIFIER
ISOLATION
Z2
-
Z1
+ REF
FIGURE 7. FEEDBACK CONTROL LOOP
15
FN9110.6
March 5, 2008