ISL6721ABZ-T Datasheet, PDF (14/22 Pages) Intersil Corporation – Flexible Single-ended Current Mode PWM Controller

ISL6721
To minimize the transformer leakage inductance, the primary
was split into two sections connected in parallel and
positioned such that the other windings were sandwiched
between them. The output windings were configured so that
the 1.8V winding is a tap off of the 3.3V winding. Tapping the
1.8V output requires that the shared portion of the
secondary conduct the combined current of both outputs.
The secondary wire gauge must be selected accordingly.
The determination of current carrying capacity of wire is a
compromise between performance, size, and cost. It is
affected by many design constraints such as operating
frequency (harmonic content of the waveform) and the
winding proximity/geometry. It generally ranges between 250
and 1000 circular mils per ampere. A circular mil is defined
as the area of a circle 0.001” (1 mil) in diameter. As the
frequency of operation increases, the AC resistance of the
wire increases due to skin and proximity effects. Using
heavier gauge wire may not alleviate the problem. Instead
multiple strands of wire in parallel must be used. In some
cases, Litz wire is required.
The winding configuration selected is:
Primary #1: 40T, 2 #30 bifilar
Secondary: 5T, 0.003” (3 mil) copper foil tapped at 3T
Bias: 17T #32
Primary #2: 40T, 2 #30 bifilar
The internal spacing and insulation system was designed for
1500VDC dielectric withstand rating between the primary
and secondary windings.
Power MOSFET Selection
Selection of the main switching MOSFET requires
consideration of the voltage and current stresses that will be
encountered in the application, the power dissipated by the
device, its size, and its cost.
The input voltage range of the converter is 36VDC to
75VDC. This suggests a MOSFET with a voltage rating of
150V is required due to the flyback voltage likely to be seen
on the primary of the isolation transformer.
The losses associated with MOSFET operation may be
divided into three categories: conduction, switching, and
gate drive.
The conduction losses are due to the MOSFET’s ON
resistance.
Pcond = r_DS(ON) • Iprms²
W
(EQ. 18)
where r_DS(ON) is the ON resistance of the MOSFET and
Iprms is the RMS primary current. Determining the
conduction losses is complicated by the variation of r_DS(ON)
with temperature. As junction temperature increases, so
does r_DS(ON), which increases losses and raises the
junction temperature more, and so on. It is possible for the
device to enter a thermal runaway situation without proper
heatsinking. As a general rule of thumb, doubling the +25°C
r_DS(ON) specification yields a reasonable value for
estimating the conduction losses at +125°C junction
temperature.
The switching losses have two components, capacitive
switching losses and voltage/current overlap losses. The
capacitive losses occur during turn on of the device and may
be calculated in Equation 19:
Pswcap
=
1_--
2
•
C
f
e
t
•
V
i
n²
•
f_s
w
W
(EQ. 19)
where Cfet is the equivalent output capacitance of the
MOSFET. Device output capacitance is specified on
datasheets as Coss and is non-linear with applied voltage.
To find the equivalent discrete capacitance, Cfet, a charge
model is used. Using a known current source, the time
required to charge the MOSFET drain to the desired
operating voltage is determined and the equivalent
capacitance may be calculated in Equation 20:
Cfet
=
-^I--^c---^h----^g-----^•----^t
V
F
(EQ. 20)
The other component of the switching loss is due to the
overlap of voltage and current during the switching
transition. A switching transition occurs when the MOSFET
is in the process of either turning on or off. Since the load is
inductive, there is no overlap of voltage and current during
the turn on transition, so only the turn off transition is of
significance. The power dissipation may be estimated using
Equation 21:
P_sw
≈
1_--
x
•
I_P
P
K
•
V_I
N
•
t_O
L
•
f_s
w
(EQ. 21)
where t_OL is the duration of the overlap period and x ranges
from about 3 through 6 in typical applications and depends
on where the waveforms intersect. This estimate may predict
higher dissipation than is realized because a portion of the
turn off drain current is attributable to the charging of the
device output capacitance (Coss) and is not dissipative
during this portion of the switching cycle.
Ip p k
V _D-S
Tol
FIGURE 6. SWITCHING CYCLE
The final component of MOSFET loss is caused by the
charging of the gate capacitance through the device gate
resistance. Depending on the relative value of any external
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FN9110.6
March 5, 2008