ISL1209_06 Datasheet, PDF (15/24 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM and Event Detection

ISL1209
EVENT INPUT TIME BASE HYSTERESIS SELECTION
BITS (EHYS<1:0>)
These two bits select the time base hysteresis of the EVIN
pin to filter bouncing or noise of external event detection
circuits. The time filter can be set between 0 to 31.25 ms.
TABLE 11.
EHYS1
EHYS0
Time Base Hysteresis
0
0
0 (pullup always on)
0
1
3.9ms
1
0
15.625ms
1
1
31.25ms
NOTE: In order to use time-based hysteresis, the sampling mode
must be enabled.
EVENT DETECT ENABLE BIT (EVEN)
This bit enables/disables the Event Detect function of the
ISL1209. When this bit is set to “1”, the Event Detect is
active. When this bit is cleared to “0”, the Event Detect is
disabled.
RTC HALT ON EVENT DETECT BIT (RTCHLT)
This bit sets the RTC registers to continue or halt counting
upon an Event Detect triggered by the EV pin. The time
keeping function will cease when RTCHLT is set to “1”, the
RTC will discontinue incrementing if an event is detected.
Counting will resume when there is a valid write to the to the
RTC registers (i.e. time set). The RTCHLT is cleared to “0”
after the write to the RTC registers.
Note: This function requires that the event detection is
enabled (see EVEN bit).
EVENT OUTPUT IN BATTERY MODE ENABLE BIT
(EVBATB)
This bit enables/disables the EVDET pin during battery
backup mode (i.e. V_BAT pin supply ON). When the EVBATB
is set to “1”, the Event Detect Output is disabled in battery
backup mode. When the EVBATB is cleared to “0”, the Event
Detect output is enabled in battery backup mode.This
feature can be used to save power during battery mode.
EVENT CURRENT SOURCE ENABLE BIT (EVIENB)
This bit enables/disables the internal pullup current source
used for the EVIN pin. When the EVIENB bit is set to “1”, the
pullup current source is always disabled. When the EVIENB
bit is cleared to “0”, the pullup current source is enabled
(current source is approximately 1µA).
Analog Trimming Register
ANALOG TRIMMING REGISTER (ATR<5:0>)
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
X1
C_X1
X2
C_X2
Crystal
Oscillator
FIGURE 11. DIAGRAM OF ATR
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34 to
+80ppm to the nominal frequency compensation. The
combination of analog and digital trimming can give up to -94
to +140ppm of total adjustment.
The effective on-chip series load capacitance, C_LOAD,
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). C_LOAD is changed via two digitally
controlled capacitors, C_X1 and C_X2, connected from the X1
and X2 pins to ground (see Figure 11). The value of C_X1 and
C_X2 is given by the following formula:
CX = (16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9)pF
The effective series load capacitance is the combination of
C_X1 and C_X2:
CLOAD
=
----------------¹------------------
⎛
⎝
-----¹-----
C_X1
+
C^-----1_X^----₂^{-⎠⎞}
CLOAD
=
⎛
⎝
1_---6_-----⋅_---b_---5_----+_-----8_----⋅_---b_---4_-----+_----4_----⋅_---b_----3_----+_----2_-2----⋅_---b_---2_----+_----1_-----⋅_---b_---1_----+_-----0_---._-5_-----⋅_--b_----0_----+_----9_{--⎠⎞}
p
F
For example, C_LOAD(ATR=00000) = 12.5pF,
C_LOAD(ATR=100000) = 4.5pF, and C_LOAD(ATR=011111) =
20.25pF. The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps.
Note that these are typical values.
BATTERY MODE ATR SELECTION (BMATR <1:0>)
Since the accuracy of the crystal oscillator is dependent on
the V_DD/V_BAT operation, the ISL1209 provides the capability
to adjust the capacitance between V_DD and V_BAT when the
device switches between power sources.
15
FN6109.4
October 17, 2006