ISL1209_06 Datasheet, PDF (14/24 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM and Event Detection

ISL1209
AUTO RESET ENABLE BIT (ARST)
This bit enables/disables the automatic reset of the BAT and
ALM status bits only. When ARST bit is set to “1”, these
status bits are reset to “0” after a valid read of the respective
status register (with a valid STOP condition). When the
ARST is cleared to “0”, the user must manually reset the
BAT and ALM bits.
INTERRUPT CONTROL REGISTER (INT)
TABLE 7. INTERRUPT CONTROL REGISTER (INT)
ADDR 7 6
5
4
3210
08h
IM ALME LPMODE FOBATB FO3 FO2 FO1 FO0
Default 0 0
0
0
0000
FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function and
select the output frequency at the IRQ/F_OUT pin. See
Table 8 for frequency selection. When the frequency mode is
enabled, it will override the alarm mode at the IRQ/F_OUT pin.
TABLE 8. FREQUENCY SELECTION OF F_OUT PIN
FREQUENCY,
F_OUT
UNITS
0
Hz
FO3
0
FO2 FO1 FO0
0
0
0
32768
Hz
0
0
0
1
4096
Hz
0
0
1
0
1024
Hz
0
0
1
1
64
Hz
0
1
0
0
32
Hz
0
1
0
1
16
Hz
0
1
1
0
8
Hz
0
1
1
1
4
Hz
1
0
0
0
2
Hz
1
0
0
1
1
Hz
1
0
1
0
1/2
Hz
1
0
1
1
1/4
Hz
1
1
0
0
1/8
Hz
1
1
0
1
1/16
Hz
1
1
1
0
1/32
Hz
1
1
1
1
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the F_OUT/IRQ pin during battery
backup mode (i.e. V_BAT power source active). When the
FOBATB is set to “1” the F_OUT/IRQ pin is disabled during
battery backup mode. This means that both the frequency
output and alarm output functions are disabled. When the
FOBATB is cleared to “0”, the F_OUT/IRQ pin is enabled
during battery backup mode.
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
V_BAT supply will be used when V_DD < V_BAT - V_BATHYS and
V_DD < V_TRIP. With LPMODE = “1”, the device will be in low
power mode and the V_BAT supply will be used when
V_DD < V_BAT - V_BATHYS. There is a supply current saving of
about 600nA when using LPMODE = “1” with V_DD = 5V.
(See Typical Performance Curves: I_DD vs VDD with
LPMODE ON & OFF.)
ALARM ENABLE BIT (ALME)
This bit enables/disables the alarm function. When the ALME
bit is set to “1”, the alarm function is enabled. When the ALME
is cleared to “0”, the alarm function is disabled. The alarm
function can operate in either a single event alarm or a periodic
interrupt alarm (see IM bit).
NOTE: When the frequency output mode is enabled, the alarm function
is disabled.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ/F_OUT pin when the RTC is
triggered by the alarm as defined by the alarm registers (0Ch
to 11h). When the IM bit is cleared to “0”, the alarm will
operate in standard mode, where the IRQ/F_OUT pin will be
tied low until the ALM status bit is cleared to “0”.
TABLE 9.
IM BIT
INTERRUPT/ALARM FREQUENCY
0
Single Time Event Set By Alarm
1
Repetitive/Recurring Time Event Set By Alarm
EVENT DETECTION REGISTER (EV)
The ISL1209 provides an easy to use event and tamper
detection circuit. The Event Detection Register configures
the functionality of the event detection circuits.
EVENT INPUT SAMPLING SELECTION BITS
(ESMP<1:0>)
These two bits select the rate of sampling of the EVIN pin to
trigger an event detection. For example, a 2Hz sampling rate
would configure the ISL1209 to check the status of the EV
pin twice a second. Slower sampling significantly reduces
the supply current drain.
TABLE 10.
ESMP1
ESMP0
EVENT SAMPLING RATE
0
0
Always ON
0
1
2Hz
1
0
1
1
1Hz
1_/4Hz
14
FN6109.4
October 17, 2006