ISL1209_06 Datasheet, PDF (12/24 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM and Event Detection

ISL1209
TABLE 5. REGISTER MEMORY MAP
BIT
REG
ADDR. SECTION NAME
7
6
5
4
3
2
00h
SC
0
SC22
SC21
SC20
SC13
SC12
01h
MN
0
MN22 MN21 MN20 MN13 MN12
02h
HR
MIL
0
HR21 HR20 HR13 HR12
03h
RTC
DT
0
0
DT21
DT20
DT13
DT12
04h
MO
0
0
0
MO20 MO13 MO12
05h
YR
YR23
YR22
YR21
YR20
YR13
YR12
06h
DW
0
0
0
0
0
DW2
07h
SR ARST XTOSCB Reserved WRTC
EVT
ALM
08h
INT
IM
ALME LPMODE FOBATB FO3
FO2
Control
09h
and
EV EVIENB EVBATB RTCHLT EVEN EHYS1 EHYS0
Status
0Ah
ATR BMATR1 BMATR0 ATR5
ATR4
ATR3
ATR2
0Bh
DTR Reserved
DTR2
0Ch
SCA ESCA ASC22 ASC21 ASC20 ASC13 ASC12
0Dh
MNA EMNA AMN22 AMN21 AMN20 AMN13 AMN12
0Eh
HRA EHRA
Alarm
0Fh
DTA EDTA
0
AHR21 AHR20 AHR13 AHR12
0
ADT21 ADT20 ADT13 ADT12
10h
MOA EMOA
0
0
AMO20 AMO13 AMO12
11h
DWA EDWA
0
0
0
0
ADW12
12h
USR1 USR17 USR16 USR15 USR14 USR13 USR12
User
13h
USR2 USR27 USR26 USR25 USR24 USR23 USR22
1
SC11
MN11
HR11
DT11
MO11
YR11
DW1
BAT
FO1
ESMP1
ATR1
DTR1
ASC11
AMN11
AHR11
ADT11
AMO11
ADW11
USR11
USR21
0
SC10
MN10
HR10
DT10
MO10
YR10
DW0
RTCF
FO0
ESMP0
ATR0
DTR0
ASC10
AMN10
AHR10
ADT10
AMO10
ADW10
USR10
USR20
RANGE DEFAULT
0-59
00h
0-59
00h
0-23
00h
1-31
00h
1-12
00h
0-99
00h
0-6
00h
N/A
01h
N/A
00h
N/A
00h
N/A
00h
N/A
00h
00-59
00h
00-59
00h
0-23
00h
1-31
00h
1-12
00h
0-6
00h
N/A
00h
N/A
00h
12
FN6109.4
October 17, 2006