X40420 Datasheet, PDF (14/25 Pages) Xicor Inc. – Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch

X40420, X40421
Figure 15. Random Address Read Sequence
S
S
Signals from ^t
Slave
the Master
a
r
Address
t
Byte
Address
t
Slave
a _Address
r
t
S
t
o
p
SDA Bus
101 00 0
1
Signals from
the Slave
A
A
C
C
K
K
A
C
K
Data
Figure 16. X40410/11 Addressing
Slave Byte
General Purpose Memory _{1 0 1 0 0 0 A8 R/W}
Control Register
1 0 1 1 0 0 1 R/W
Fault Detection Register 1 0 1 1 0 0 0 R/W
Word Address
General Purpose Memory _{A7 A6 A5 A4 A3 A2 A1 A0}
Control Register
111 11111
Fault Detection Register 1 1 1 1 1 1 1 1
Word Address
The word address is either supplied by the master or
obtained from an internal counter.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for t_PURST.
Figure 17. Sequential Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
Slave
Address
A
C
K
1
A
C
K
Data
(1)
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
S
t
o
A
A
p
C
C
K
K
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
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March 28, 2005