X40420 Datasheet, PDF (1/25 Pages) Xicor Inc. – Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch

®
PRELIMINARY
Data Sheet
X40420, X40421
4kbit EEPROM
March 28, 2005
FN8117.0
Dual Voltage Monitor with Integrated CPU
Supervisor and System Battery Switch
FEATURES
• Dual voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
—V_TRIP2 Programmable down to 0.9V
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to V_CC = 1V
—Monitor two voltages or detect power fail
• Battery Switch Backup
• V_OUT: 5mA to 50mA from V_CC; or 250µA from
V_BATT
• Fault detection register
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
—1µA typical battery current in backup mode
• 4Kbits of EEPROM
—16 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0 or 1/2, of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
• •Monitor Voltages: 5V to 1.6V
• Memory Security
• Battery Switch Backup
• V_OUT 5mA to 50mA
APPLICATIONS
• Communications Equipment
—Routers, Hubs, Switches
—Disk arrays
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
—Desktop Computers
—Network Servers
X40420/21
Standard V_TRIP1 Level Standard V_TRIP2 Level
4.6V (+/-1%)
2.9V(+/-1.7%)
4.6V (+/-1%)
2.6V (+/-2%)
2.9V(+/-1.7%)
1.6V (+/-3%)
See “Ordering Information” for more details
For Custom Settings, call Intersil.
Suffix
-A
-B
-C
DESCRIPTION
The X40420/21 combines power-on reset control,
watchdog timer, supply voltage supervision, and sec-
ondary supervision, manual reset, and Block Lock^™
protect serial EEPROM in one package. This combi-
nation lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to V_CC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
BLOCK DIAGRAM
V2MON
V2 Monitor
Logic
V_OUT
+
V_TRIP2
-
V2FAIL
SDA
WP
SCL
V_CC
(V1MON)
BATT-ON
V_OUT
V_BATT
Data
Register
Command
Decode Test
& Control
Logic
System
Battery
Switch
Fault Detection
Register
Status
Register
EEPROM
Array
V_{CCLMogoicnitor}
V_OUT
+
V_TRIP1
-
Watchdog
and
Reset Logic
V_OUT
Power-on,
Manual Reset
Low Voltage
Reset
Generation
WDO
MR
RESET
X40420
RESET
X40421
LOWLINE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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