ISL78419_15 Datasheet, PDF (14/20 Pages) Intersil Corporation – Integrated Automotive TFT-LCD Power Supply Regulator

ISL78419
The Access Control Register (ACR) determines which word at
address 00h is accessed (IVR or WR). The volatile ACR must be
set as follows:
• When the ACR is all zeroes, which is the default at power-up:
- A read operation to address 0 outputs the value of the
non-volatile IVR
- A write operation to address 0 writes the identical values to
the WR and IVR of the DCP
• When the ACR is 80h:
- A read operation to address 0 outputs the value of the
volatile WR
- A write operation to address 0 only writes to the volatile WR
It is not possible to write to an IVR without writing the same value
to its WR.
00h and 80h are the only values that should be written to
address 2. All other values are reserved and must not be written
to address 2.
TABLE 6. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
2
-
ACR
1
Reserved
0
IVR
WR
WR: Wiper Register, IVR: Initial Value Register.
I²C Serial Interface
The ISL78419 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data on to the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is a master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the DCP of the ISL78419 operates as a slave device in
all applications. The fall and rise time of SDA and SCL signal
should be in the range listed in Table 8. Capacitive load on I²C
bus is also specified in Table 8.
All communication over the I²C interface is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. The SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 15). On
power-up of the ISL78419, the SDA pin is in the input mode.
All I²C interface operations must begin with a START condition,
which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The
DCP continuously monitors the SDA and SCL lines for the START
condition and does not respond to any command until this
condition is met (see Figure 15). A START condition is ignored
during the power-up sequence and during internal non-volatile
write cycles.
All I²C interface must be terminated by a STOP condition, which
is a LOW-to-HIGH transition of SDA while SCL is high (see
Figure 15). A STOP condition at the end of a read operation, or at
the end of a write operation to volatile bytes only places the
device in its standby mode. A STOP condition during a write
operation to a non-volatile write byte, initiates an internal
non-volatile write cycle. The device enters its standby state when
the internal non-volatile write cycle is completed.
An ACK (Acknowledge) is a software convention used to indicate a
successful data transfer. The transmitting device, either master or
slave, releases the SDA bus after transmitting eight bits. During the
ninth clock cycle, the receiver pulls the SDA line LOW to
acknowledge the reception of the eight bits of data (see Figure 16).
The ISL78419 DCP responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and once
again after successful receipt of an Address Byte. The ISL78419
also responds with an ACK after receiving a Data Byte of a write
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
A valid Identification Byte contains 0101000 as the seven MSBs.
The LSB is in the Read/Write bit. Its value is "1" for a Read
operation, and "0" for a Write operation (see Table 7).
0
(MSB)
TABLE 7. IDENTIFICATION BYTE FORMAT
101000
R/W
(LSB)
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
FIGURE 15. VALID DATA CHANGES, START AND STOP CONDITIONS
STOP
Submit Document Feedback ₁₄
FN8292.3
June 27, 2014