ISL78419_15 Datasheet, PDF (13/20 Pages) Intersil Corporation – Integrated Automotive TFT-LCD Power Supply Regulator

VIN
UVLO
THRESHOLD
0
VGH
RESET
ISL78419
VDPM
1.215V
VFLK
VGHM
VGH
V_GHM IS FORCED
GPM_LO
TO V_GH WHEN V_IN
FALLS TO UVLO AND
SSLloOpPe Eis IcSontrolled
V_GH > 3V
C_bO_y N_RETROLLED BY RE
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FIGURE 14. GATE PULSE MODULATOR TIMING DIAGRAM
Gate Pulse Modulator Circuit
The gate pulse modulator circuit functions as a three way
multiplexer, switching V_GHM between ground, GPM_LO and V_GH.
Voltage selection is provided by digital inputs VDPM (enable) and
VFLK (control). High-to-low delay and slew control is provided by
external components on pins CE and RE, respectively.
When VDPM is LOW, the block is disabled and VGHM is
grounded. When the input voltage exceeds UVLO threshold,
VDPM starts to drive an external capacitor. Once VDPM exceeds
1.215V, the GPM circuit is enabled, and the output VGHM is
determined by VFLK, RESET signal and V_GH voltage. If the RESET
signal is high and VFLK is high, V_GHM is pulled to V_GH. When
VFLK goes low, there is a delay controlled by capacitor CE,
following which, V_GHM is driven to GPM_LO, with a slew rate
controlled by resistor RE. Note that GPM_LO is used only as a
reference voltage for an amplifier, and thus does not have to
source or sink a significant DC current.
Low-to-High transition is determined primarily by the switch
resistance and the external capacitive load. High-to-low transition
is more complex. Take the case where the block is already
enabled (VDPM is high). When VFLK is high, if CE is not externally
pulled above threshold voltage 1, pin CE is pulled low. On the
falling edge of VFLK, a current is passed into pin CE to charge the
external capacitor up to threshold voltage 2, providing a delay
which is adjustable by varying the capacitor on CE. Once this
threshold is reached, the output starts to be pulled down from
V_GH to GPM_LO. The maximum slew current is equal to
500/(RE + 40k), and the dv/dt slew rate is Isl/C_LOAD, where
C_LOAD is the load capacitance applied to V_GHM. The slew rate
reduces as V_GHM approaches GPM_LO.
If CE is always pulled up to a voltage above threshold 1, zero
delay mode is selected; thus there will be no delay from FLK
falling to the point where V_GHM starts to fall. Slew down currents
will be identical to the previous case.
At power-down, when V_IN falls to UVLO, V_GHM will be tied to V_GH
until the V_GH voltage falls to 3V. Once the V_GH voltage falls below
3V, V_GHM will not be actively driven until V_IN is driven. Figure 14
shows the V_GHM voltage based on V_IN, V_GH and RESET.
VCOM Amplifier
The VCOM amplifier is designed to control the voltage on the
back plane of an LCD display. This plane is capacitively coupled
to the pixel drive voltage, which alternately cycles positive and
negative at the line rate for the display. Thus, the amplifier must
be capable of sourcing and sinking pulses of current, which can
occasionally be quite large (in the range of 100mA for typical
applications).
The ISL78419 VCOM amplifier's output current is limited to
225mA typical. This limit level, which is roughly the same for
sourcing and sinking, is included to maintain reliable operation
of the part. It does not necessarily prevent a large temperature
rise if the current is maintained. (In this case, the whole chip may
be shut down by the thermal trip to protect functionality.) If the
display occasionally demands current pulses higher than this
limit, the reservoir capacitor will provide the excess and the
amplifier will top the reservoir capacitor back up once the pulse
has stopped. This will happen in the µs time scale in practical
systems and for pulses 2 or 3 times the current limit; the VCOM
voltage will have settled again before the next line is processed.
DCP Memory Description
The ISL78419 contains 1 non-volatile byte known as the Initial
Value Register (IVR). It is accessed by the I²C interface
operations with Address 00h. The IVR contains the value that is
loaded into the volatile Wiper Register (WR) at power-up.
The volatile WR, and the non-volatile IVR of a DCP are accessed
with the same address.
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FN8292.3
June 27, 2014