ISL6569A Datasheet, PDF (14/22 Pages) Intersil Corporation – Multi-Phase PWM Controller

ISL6569A
Following the delay, the soft start ramps linearly until V_RAMP
reaches VID. For the system described above, this first linear
ramp will continue for approximately
t_RAMP1
=
T----_{S----S-- –}
1.4
t_DELAY
= 5.27ms
(EQ. 11)
The final portion of the soft-start sequence is the time
remaining after V_RAMP reaches VID and before I_RAMP gets to
zero. This is also characterized by a slight change in the slope
of the output voltage ramp which, for the current example,
exists for a time of
t_RAMP2 = T_SS – t_RAMP1 – t_DELAY
= 2.34ms
(EQ. 12)
This behavior is seen in the example in Figure 10 of a converter
switching at 500kHz. For this converter, R_FB is set to 2.67kΩ
leading to T_SS = 4.0ms, t_DELAY = 700ns, t_RAMP1 = 2.23ms,
and t_RAMP2 = 1.17ms.
VOUT, 500mV/DIV
EN, 5V/DIV
t_DELAY t_RAMP1 t_RAMP2
1ms/div
FIGURE 10. SOFT-START WAVEFORMS FOR ISL6569A
BASED MULTI-PHASE BUCK CONVERTER
NOTE: Switching frequency 500kHz and R_FB = 2.67kΩ
Fault Monitoring and Protection
The ISL6569A actively monitors voltage and current
feedback to detect fault conditions. Fault monitors trigger
protective measures to prevent damage to a microprocessor
load. One common power good indication signal is provided
for linking to external system monitors. The schematic in
Figure 11 outlines the interaction between the fault monitors
and the power good signal.
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
which indicates that the converter is operating properly and
the output voltage is within a set window. The under-voltage
(UV) and over-voltage (OV) comparators create the output
voltage window. The controller also takes advantage of
current feedback to detect output over-current (OC)
PGOOD
UV
DAC
REFERENCE
+
350mV
-
POR
CIRCUIT
VDIFF
+
OV
-
-
OC
+
90µA
I_AVG
OVP
2.2V
FIGURE 11. POWER GOOD AND PROTECTION CIRCUITRY
conditions. PGOOD pulls low during shutdown and releases
high during soft-start once the output voltage exceeds the
UV threshold. Once high, PGOOD will only transition low
when the controller is disabled or a fault condition is
detected. It will return high under certain circumstances
once a fault clears.
Under-Voltage Protection
The voltage on V_DIFF is internally offset by 350mV before it
is compared with the DAC reference voltage. By positively
offsetting the output voltage, an UV threshold is created
which moves relative to the VID code. During soft-start, the
slow rising output voltage eventually exceeds the UV
threshold. Assuming the POR leg of the PGOOD NOR gate
has not detected an OC fault, the PGOOD signal will go
high.
If a fault condition arises during operation and the output
voltage drops below the UV threshold, PGOOD will
immediately pull low, but converter operation will continue.
PGOOD will return high once the output voltage surpasses
the UV threshold.
If the ISL6569A is disabled during operation, the PGOOD
signal will not pull low until the output voltage decays below
the UV threshold.
Over-Voltage Protection
When the output of the differential amplifier (VDIFF) reaches
2.2V, PGOOD immediately goes low indicating a fault. Two
protective actions are taken by the ISL6569A to protect the
microprocessor load.
First, all PWM outputs are commanded low. Directing the
Intersil drivers to turn on the lower MOSFETs; shunting the
output to ground preventing any further increase in output
voltage. The PWM outputs remain low until VDIFF falls to the
programmed DAC level at which time they go into a high-
14
FN9092.2
December 29, 2004