ISL6296 Datasheet, PDF (14/17 Pages) Intersil Corporation – FlexiHash For Battery Authentication

ISL6296
ADDRESS
1-00
1-01
ADDRESS
2-00
2-01
2-05
NAME
MSCR
STAT
NAME
SESL
CHLG
AUTH
TABLE 9. CONTROL AND STATUS REGISTERS (BANK 1)
DESCRIPTION
BIT 7 BIT 6 BIT 5 BIT 4 BIT3 BIT 2
Master Control
eEEW eINT
--
--
--
--
Device Status
sEEW sBER sACC
--
DAB[1:0]
TABLE 10. AUTHENTICATION REGISTERS (BANK 2)
DESCRIPTION
BIT 7 BIT 6 BIT 5 BIT 4 BIT3 BIT 2
Secrets Selection
--
--
--
--
CSL[1:0]
Challenge Code Register
CHLG[31:0]
Authentication Code Register
AUTH[7:0]
BIT 1 BIT 0
ASLP SRST
SLO[1:0]
BIT 1 BIT 0
SSL[1:0]
BIT
NAME
7:6 DAB[1:0]
5:4 SPD[1:0]
3
eINT
2
ASLP
1:0 SLO[1:0]
TYPE
RW
RW
RW
RW
RW
TABLE 11. DEFAULT CONFIGURATION (DCFG) REGISTER SETTINGS
DEFAULT
DESCRIPTION
00
Device Address Bit Setting:
00 : device responds only when CS field in instruction frame is’0’
01 : device responds to any CS field value in instruction frame
10 : device responds to any CS field value in instruction frame
11 : device responds only when CS field in instruction frame is ‘1’
01
XSD Bus Speed Setting: Configures the bit rate of the XSD bus interface.
00 : 0.5x (2.89kbps)
01 : 1x (5.78kbps)
10 : 2x (11.56kbps)
11 : 4x (23.12kbps)
1
Power-on default setting of eINT bit in the MSCR register.
1
Power-on default setting of ASLP bit in the MSCR register.
00
Secrets Lock-out Bits:
Bit 1 : Read/Write lock-out bit for address locations 0-02 to 0-09 (Secret Set #1 & #2)
Bit 0 : Read/Write lock-out bit for address locations 0-0A to 0-0D (Secret Set #3)
NOTE: Once Bit 0 or Bit 1 is set, writing to the OTP ROM will permanently be disabled
(after a reset cycle).
BIT
NAME
7
HSF
6:4 TIBB[2:0]
3:0 TOSC[3:0]
TYPE
R
R
R
TABLE 12. DEFAULT TRIMMING (DTRM) REGISTER SETTINGS
DEFAULT
DESCRIPTION
0
Unused
--
Reference Current Trim Setting
--
Oscillator Frequency Trim Setting
TABLE 13. LEGEND FOR THE TYPE COLUMN
TYPE
READ ACTION
WRITE ACTION
R Read-only
Data read
Data ignored
W Write-only
Zeros read
Data written
RW Read/Write
Data read
Data written
RC Clear after read Data read, then
cleared
Data ignored
WC Clear after write Zeros read
Data written, then
cleard
<> Default setting loaded from designated OTP ROM bit
locations
W Writing disabled after lock-out
ADDRESS 0-00: DEFAULT CONFIGURATION (DCFG)
This address location stores the default configuration when
the ISL6296 is manufactured. Table 11 describes each bit in
detail. The legend for the TYPE column is given in Table 13.
ADDRESS 0-01: DEFAULT TRIM SETTING (DTRM)
This address location is writable only when the device is in
test mode. During normal operation, any data written to it will
be ignored. Table 12 describes the DTRM address in detail.
ADDRESS 0-02/03/04/05: AUTHENTICATION SECRET
SET #1 (SE1A/B/C/D)
These address locations store the first set of secrets to be
used for hash calculation. Reading and writing to this
register can be disabled by setting the SLO[1] bit at OTP
ROM location 0-00[1].
14
FN9201.0
February 1, 2005