ISL6296 Datasheet, PDF (12/17 Pages) Intersil Corporation – FlexiHash For Battery Authentication

ISL6296
Bus Transaction Protocol
The XSD bus for the ISL6296 defines three types of bus
transactions. Figure 11 shows the bus transaction protocol.
The blue color represents the signal sent by the host and the
green color stands for the signal sent by the device. Before
the transaction starts, the host should make sure that the
XSD device is not in the sleep mode. One method is to
always send a ‘break’ signal before starting the transaction,
as shown in Figure 11. If the device is not in the sleep mode,
the ‘break’ signal is not mandatory. The ‘break’ pulse width
may appear to be wider than what the host sends out
because of the reason explained in Figure 4. The symbols in
Figure 11 are explained in Table 7.
TABLE 7. SYMBOLS IN THE BUS TRANSACTION PROTOCOL
SYM
DESCRIPTION
MIN TYP MAX
IFG_H Host inter-frame gap
IFG_D Device inter-frame gap
TA_H Host turn-around time
TA_D Device turn-around time
0 BT_H
800ms
1 BT_D
1 BT_H
800ms
1 BT_D
Passive CRC Support
The CRC feature only supports the read transaction in the
ISL6296. When the OPCODE in the instruction is ‘10’, an
8-bit CRC is automatically calculated for the data bytes
being transferred out. The CRC result is then appended after
the last data byte is read out.
CRC is generated using the DOW CRC polynomial as
follows:
Polynom = 1 + X⁴ + X⁵ + X⁸
The CRC generation algorithm is logically illustrated in
Figure 12. Prior to a new CRC calculation, the LFSR (linear
feedback shift register) is initialized to zero. The read data to
be transmitted out is concurrently shifted into the CRC
calculator. After the actual data is transmitted out, the final
content of the LFSR is the resulting CRC value. This value is
transmitted out after the read data, with LSB being
transmitted out first.
(A) Multi-Byte Write Instruction.
break
T_SD
Write Instruction Frame
IFGH
Data Frame 1
IFGH
Data Frame 2
(B) Multi-Byte Read Instruction.
break
T_SD
Read Instruction Frame
TA _D
Data Frame 1
(output from slave)
IFG _D
Data Frame 2
(output from slave)
(C) Back-to-Back Transaction (Read Followed by Write).
break
T_SD
Read Instruction Frame
TA _D
Data Frame
(output from slave)
TA _H
Next Instruction
Frame
FIGURE 11. XSD BUS TRANSACTION PROTOCOL. THE ‘BREAK’ SIGNAL IS OPTIONAL IF THE DEVICE IS AWAKE
Serial
Output
1st
Stage
LSB
2nd
Stage
3rd
Stage
4th
Stage
5th
Stage
6th
Stage
7th
Stage
FIGURE 12. THE CRC CALCULATOR FOR THE PASSIVE CRC SUPPORT
8th
Stage
MSB
12
FN9201.0
February 1, 2005