ISL6296 Datasheet, PDF (13/17 Pages) Intersil Corporation – FlexiHash For Battery Authentication

ISL6296
Analog Biasing Components and Clock
Generation
The analog section in the ISL6296 mainly includes the Time
Base Generator and the internal regulator for powering the
circuits in the ISL6296.
TIME BASE GENERATOR
A time base generator is included on-chip to provide timing
reference for serial data encoding and decoding at the XSD
bus interface. This eliminates the need for an external
crystal. The time base oscillator is trimmed during
manufacturing to a nominal frequency of 532.5kHz. It has a
frequency tolerance better than 5% over operating supply
voltage and temperature range.
INTERNAL VOLTAGE REGULATOR
The ISL6296 incorporates an internal voltage regulator that
maintains a nominal operating voltage of 2.5V within the
device. The regulator draws power directly from the VDD
input. No external component is required to regulate circuit
voltage. The regulator is shut off during Sleep mode.
Memory/Operational Register Description
The ISL6296 memory and register structure is organized into
4 banks of 256 addressable locations. However, not all of the
addressable registers are used nor implemented. Accessing
an unimplemented register will result in the access
instruction being ignored. A bus error indication may or may
not be flagged.
Bank 0 is dedicated for the OTP ROM. There are 16 memory
locations implemented in the array. Writing to the OTP ROM
has no immediate effect on the chip operation until a Power-
on Reset occurred, or a soft reset is issued. Table 8
describes the OTP ROM memory assignment. The default
factory setting for address [0:00] is given in Table 11.
Bank 1 contains the Control and Status registers. Only 2
registers are implemented. Table 9 shows the register map
of the Bank 1 registers. Detailed description of register
settings is given in Table 14 and 15.
Bank 2 contains the Authentication registers. Only 3
registers are implemented. These registers are used during
the battery pack authentication process. Table 10 describes
the mapping of the Authentication registers.
Bank 3 is reserved for Intersil production testing only, and
will not be accessible during normal operation. Accessing
the Test and Trim Registers when not in test mode will result
in a bus error.
TABLE 8. OTP ROM MEMORY MAP (BANK 0)
ADDRESS NAME
DESCRIPTION
BIT 7 BIT 6 BIT 5 BIT 4 BIT3 BIT 2 BIT 1 BIT 0
0-00
DCFG
Default Configuration
DAB[1:0]
SPD[1:0]
eINT ASLP
SLO[1:0]
0-01
DTRM
Default Trimming
HSF
TIBB[2:0]
TOSC[3:0]
0-02
SE1A
Auth Secret #1A
S1A[7:0]
0-03
SE1B
Auth Secret #1B
S1B[7:0]
0-04
SE1C
Auth Secret #1C
S1C[7:0]
0-05
SE1D
Auth Secret #1D
S1D[7:0]
0-06
SE2A
Auth Secret #2A
S2A[7:0]
0-07
SE2B
Auth Secret #2B
S2B[7:0]
0-08
SE2C
Auth Secret #2C
S2C[7:0]
0-09
SE2D
Auth Secret #2D
S2D[7:0]
0-0A
SE3A
Auth Secret #3A
S3A[7:0]
0-0B
SE3B
Auth Secret #3B
S3B[7:0]
0-0C
SE3C
Auth Secret #3C
S3C[7:0]
0-0D
SE3D
Auth Secret #3D
S3D[7:0]
0-0E
0-0F
INF1
INF2
General Purpose
General Purpose
General purpose non-volatile memory for storage of model ID, date code, and other
cell information
NOTE: Information stored in address 0-0E (INF1) and 0-0F (INF2) is for use by the host firmware only. Actual content depends on the host firmware
customization preference.
13
FN9201.0
February 1, 2005