ISL6227 Datasheet, PDF (14/27 Pages) Intersil Corporation – Dual Mobile-Friendly PWM Controller with DDR Option

ISL6227
Theory of Operation
Operation
The ISL6227 is a dual channel PWM controller intended for
use in power supplies for graphic chipsets, SDRAM, DDR
DRAM, or other low voltage power applications in modern
notebook and sub-notebook PCs. The IC integrates two
control circuits for two synchronous buck converters. The
output voltage of each controller can be set in the range of
0.9V to 5.5V by an external resistive divider.
The synchronous buck converters can operate from either
an unregulated DC source, such as a notebook battery, with
a voltage ranging from 5.0V to 28V, or from a regulated
system rail of 3.3V or 5V. In either operational mode the
controller is biased from the +5V source.
The controllers operate in the current mode with input
voltage feed-forward which simplifies feedback loop
compensation and rejects input voltage variation. An
integrated feedback loop compensation dramatically
reduces the number of external components.
Depending on the load level, converters can operate either
in a fixed 300kHz frequency mode or in a HYS mode.
Switch-over to the HYS mode of operation at light loads
improves converter efficiency and prolongs battery life. The
HYS mode of operation can be inhibited independently for
each channel if a variable frequency operation is not
desired.
The ISL6227 has a special means to rearrange its internal
architecture into a complete DDR solution. When the DDR
pin is set high, the second channel can provide the capability
to track the output voltage of the first channel. The buffered
reference voltage required by DDR memory chips is also
provided.
Initialization
The ISL6227 initializes if at least one of the enable pins is
set high. The Power-On Reset (POR) function continually
monitors the bias supply voltage on the VCC pin, and
initiates soft-start operation when EN1 or EN2 is high after
the input supply voltage exceeds 4.45V. Should this voltage
drop lower than 4.14V, the POR disables the chip.
Soft-Start
When soft-start is initiated, the voltage on the SOFT pin of
the enabled channel starts to ramp up gradually with the
internal 4.5µA current charging the soft-start capacitor. The
output voltage follows the soft-start voltage with the
converter operating at 300kHz PWM switching frequency.
When the SOFT pin voltage reaches 0.9V, the output voltage
comes into regulation, (see block diagram). When the SOFT
voltage reaches 1.5V, the power good (PGOOD) and the
mode control is enabled. The soft-start process is depicted in
Figure 33.
EN
1
1.5V
0.9V
SOFT
2
VOUT
3
PGOOD
4
Ch1 5.0V
Ch3 1.0V
Ch2 2.0V
Ch4 5.0V
FIGURE 33. START-UP
M1.00ms
Even though the soft-start pin voltage continues to rise after
reaching 1.5V, this voltage does not affect the output
voltage. During the soft-start, the converter always operates
in continuous conduction mode independent of the load level
or VOUT pin connection.
The soft-start time (the time from the moment when EN
becomes high to the moment when PGOOD is reported) is
determined by Equation 1:
t_SOFT = ¹----^.--⁵---^V4----_.--^×₅----_μ-^C---_A-^s----^o----^f--^t
(EQ. 1)
The time it takes the output voltage to come into regulation
can be obtained from Equation 2:
t_RISE = 0.6 × t_SOFT
(EQ. 2)
During soft-start stage before the PGOOD pin is ready, the
undervoltage protection is prohibited. The overvoltage and
overcurrent protection functions are enabled.
If the output capacitor has residue voltage before startup,
both lower and upper MOSFETs are in off-state until the
soft-start capacitor charges equal the VSEN pin voltage.
This will ensure the output voltage starts from its existing
voltage level.
14
FN9094.7
May 4, 2009