ISL6227 Datasheet, PDF (13/27 Pages) Intersil Corporation – Dual Mobile-Friendly PWM Controller with DDR Option

Block Diagram
BOOT1
UGATE1
PHASE1
PGND1
LGATE1
VCC
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
PWM/HYS TRANSITION
MODE CHANGE COMP 1
HYSTERETIC COMPARATOR 1
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO CHANGE
PWM OR HYS MODE
ΔV_HYS = 15mV
VSEN1
300kΩ
500kΩ
SOFT1
+ _0.9V
REF
1MΩ
15pF
1.25pF
4.4kΩ
ERROR AMP 1
ISEN1 ^140Ω
CURRENT
SAMPLE
OCSET1
CURRENT
SAMPLE
0.9V REFERENCE
PG1 EN1 VOUT1
VCC GND
VOUT2 EN2 REF/PG2
BOOT2
UGATE2
DDR = 0 ^{DDR = 1}
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
PWM/HYS TRANSITION
PHASE2
PGND2
LGATE2
POR
VCC
ENABLE
MODE CHANGE COMP 2
OV UV
PGOOD
VOLTS/SEC
CLAMP
PWM1
BIAS SUPPLIES
REFERENCE
FAULT LATCH
SOFT-START
DDR MODE
CONTROL
OC1 DDR OC2
OV UV
PGOOD
VOLTS/SEC
CLAMP
PWM2
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO CHANGE
PWM OR HYS MODE
HYSTERETIC COMPARATOR 2
ΔV_HYS = 15mV
15pF
1MΩ
4.4kΩ
1.25pF
ERROR AMP 2
500kΩ
300kΩ
(200kΩ, DDR = 1)
VSEN2
SOFT2
DUTY CYCLE RAMP GENERATOR
PWM CHANNEL PHASE CONTROL
DDR EN1 EN2
VIN
CH1/CH2 φ
01
11
1
0V ⇔ 28.0V
1 ^{4.2 < VIN < 28.0V}
VIN < 4.2
180°
90°
0°
CURRENT
SAMPLE
0.9V REFERENCE ₊
DDR = 0
+
0.9V
REF
DDR = 1
140Ω _ISEN2
CURRENT
SAMPLE
OCSET2
DDR = 0
DDR = 1
OC1
OC2
1/2.9
OCSET1
1/33.1
ISEN1
VIN
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO LATCH
OVERCURRENT FAULT
DDR
VCC
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO LATCH
OVERCURRENT FAULT
1/33.1
ISEN2
1/2.9
OCSET2
DDR VREF
BUFFER AMP
DDR VTT
REFERENCE