ISL1902 Datasheet, PDF (14/25 Pages) Intersil Corporation – Full-Featured, Dimmable AC Mains LED Driver with PFC

ISL1902
Functional Description
Features
The ISL1902 LED driver is an excellent choice for low cost, AC
mains powered single conversion LED lighting applications. It
provides active power factor correction (PFC) to achieve high
power factor using critical conduction mode operation, and
incorporates additional features for compatibility with
triac-based dimmers. The ISL1902 includes support for both
PWM and DC current dimming of the output. Similar to the
ISL1901, the ISL1902 adds additional features to facilitate the
design of higher performance LED drivers.
Oscillator
The ISL1902 uses a critical conduction mode (CrCM) algorithm to
control the switching behavior of the converter. The ON-time of
the primary power switch is held virtually constant by the low
bandwidth control loop. The OFF-time duration is determined by
the time it takes the current or voltage to decay during the
flyback period. When the MMF (Magneto Motive Force) of the
magnetic element decays to zero (dB/dt=0), the winding
voltages collapse and the winding currents are zero (flyback) or
DC (SEPIC). Either may be monitored and used to initiate the next
switching cycle to achieve CrCM operation. Additionally, there is a
user adjustable threshold, DELADJ, to delay the initiation of the
next switching cycle to allow the drain-source voltage of the
primary switch to ring to a minimum. This allows quasi-ZVS
operation to reduce capacitive switching losses and improve
efficiency.
By its nature, the converter operation is variable frequency. There
are both minimum and maximum frequency clamps that limit
the range of operation. The minimum frequency clamp prevents
the converter from operating in the audible frequency range
while the maximum frequency clamp prevents operating at very
high frequencies that may result in excessive losses.
An individual switching period is the sum of the ON-time, the
OFF-time, and the restart delay duration. The ON-time is
determined by the control loop error voltage, VERR, and the
RAMP signal. As its name implies, the RAMP signal is a linearly
increasing signal that starts at zero volts and ramps to a
maximum of ~VERR/5 - 230mV. RAMP requires an external
resistor and capacitor connected to VREF to form an RC charging
network. If VERR is at its maximum level of VREF, the time
required to charge RAMP to ~850mV determines the maximum
ON-time of the converter. RAMP is discharged every switching
cycle when the ON-time terminates.
The OFF-time duration is determined by the design of the
magnetic element(s), which depends on the required energy
storage/transfer and the inductance of the windings. The
transformer/inductor design also determines the maximum
ON-time that can be supported without saturation, so, in reality,
the magnetic design is critical to every aspect of determining the
switching frequency range.
THE FLYBACK TOPOLOGY
The design methodology is similar to designing a discontinuous
mode (DCM) flyback transformer with the constraint that it must
operate at the DCM/CCM boundary at maximum load and
minimum input voltage. The difference is that the converter will
always operate at the DCM/CCM boundary, whereas a DCM
converter will be more discontinuous as the input voltage
increases or the load decreases. For PFC applications, the design
is further complicated by the input voltage waveform; a virtually
unfiltered rectified AC mains sinewave.
Once the output power, P_O, the output current, I_O, the output
voltage, V_O, and the minimum input AC voltage are known, the
transformer design can be started. From the minimum AC input
voltage, the minimum average input voltage must be
determined. The converter behaves as if the input voltage is an
equivalent DC value due to the low control loop bandwidth. P_O
determines the amount of energy that must be stored in the
transformer on each switching cycle, but must be corrected for
efficiency. This includes leakage inductance losses, winding
losses, and all secondary side losses. This can be estimated as a
portion of the total efficiency, η, or as is typically done, includes
all of the losses.
A typical minimum operating frequency and maximum duty cycle
must be selected. These are somewhat arbitrary in their
selection, but do ultimately determine core size. The typical
frequency is what occurs when the instantaneous rectified input
AC voltage is exactly at the equivalent DC value. The frequency
will be higher when the instantaneous input voltage is lower, and
lower when the instantaneous input voltage is higher. However,
the duty cycle at the equivalent DC input voltage determines the
ON-time for the entire AC half-cycle. The ON-time is constant due
to the low bandwidth control loop, but the OFF-time and duty
cycle vary with the instantaneous input voltage since the peak
switch current follows V = Ldi/dt.
The lowest frequency may require adjustment once the initial
calculations are complete to see if the operating frequency at the
peak of the minimum AC input voltage is acceptable.
P_IN = ^P--_η---^o-
W
(EQ. 1)
TABLE 1. OSCILLATOR DEFINITIONS
V_mINrms = Minimum RMS input voltage
V_maxINrms = Maximum RMS input voltage
f_typ(avg) = Typical frequency when V_IN (instantaneous) = V_IN(rms)
η = Efficiency
D_max = Maximum typical duty cycle desired
Dmin = Minimum typical duty cycle
t_ON(MAX) = f_typ(avg) x D_max
Ls = Secondary inductance
Lp = Primary inductance
Nsp = Transformer turns ratio, Ns/Np
Ip(peak) = Peak primary current within a switching cycle
t_ON ON-time of the power FET controlled by OUT
t_OFF OFF-time duration required for CrCM operation
t_DELAY = User adjustable delay before the next switching cycle
begins
14
FN7981.2
March 20, 2013