ISL12029_1012 Datasheet, PDF (14/29 Pages) Intersil Corporation – Real Time Clock/Calendar with I2C Bus™ and EEPROM

ISL12029, ISL12029A
X1
C_X1
X2
C_X2
CRYSTAL
OSCILLATOR
FIGURE 12. DIAGRAM OF ATR
The effective on-chip series load capacitance, C_LOAD,
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). C_LOAD is changed via two digitally
controlled capacitors, C_X1 and C_X2, connected from the X1
and X2 pins to ground (see Figure 11). The value of C_X1 and
C_X2 is given by Equation 1:
CX = (16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9)pF
(EQ. 1)
The effective series load capacitance is the combination of
C_X1 and C_X2 given in Equation 2:
CLOAD
=
----------------¹------------------
⎛
⎝
-----¹-----
C_X1
+
C^-----1_X^----₂^{-⎠⎞}
CLOAD
=
⎛
⎝
1_---6_-----⋅_---b_---5_----+_-----8_----⋅_---b_---4_-----+_----4_----⋅_---b_----3_----+_----2_-2----⋅_---b_---2_----+_----1_-----⋅_---b_---1_----+_-----0_---._-5_----⋅_----b_---0_----+_----9_{--⎠⎞}
p
F
(EQ. 2)
For example, CLOAD(ATR = 00000) = 12.5pF,
C_LOAD(ATR = 100000) = 4.5pF, and C_LOAD(ATR = 011111) =
20.25pF. The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps. Note
that these are typical values.
DTR Register - DTR2, DTR1, DTR0: Digital
Trimming Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
DTR2 is a sign bit. DTR2 = 0 means frequency
compensation is > 0. DTR2 = 1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10ppm
adjustment and DTR0 gives 20ppm adjustment.
A range from -30ppm to +30ppm can be represented by
using the three DTR bits.
TABLE 5. DIGITAL TRIMMING REGISTERS
DTR REGISTER
DTR2
DTR1
DTR0
ESTIMATED FREQUENCY
PPM
0
0
0
0
TABLE 5. DIGITAL TRIMMING REGISTERS (Continued)
DTR REGISTER
DTR2
DTR1
DTR0
ESTIMATED FREQUENCY
PPM
0
1
0
+10
0
0
1
+20
0
1
1
+30
1
0
0
0
1
1
0
-10
1
0
1
-20
1
1
1
-30
PWR Register: SBIB, BSW, VTS2, VTS1, VTS0
SBIB: Serial Bus Interface (Enable)
The serial bus can be disabled in battery backup mode by
setting this bit to “1”. This will minimize power drain on the
battery. The Serial Interface can be enabled in battery
backup mode by setting this bit to “0”. (default is “0”). See
“RESET” on page 9 and “Power Control Operation” on
page 16.
BSW: Power Control Bit
The Power Control bit, BSW, determines the conditions for
switching between V_DD and Back Up Battery. There are two
options.
Option 1 Standard Mode: Set “BSW = 0” (default for
ISL12029A)
Option 2 Legacy/Default Mode: Set “BSW = 1” (default for
ISL12029)
See “Power Control Operation” on page 16 for more details.
Also see “I²C Communications During Battery Backup and
LVR Operation” on page 25 for important details.
VTS2, VTS1, VTS0: V_RESET Select Bits
The ISL12029 is shipped with a default V_DD threshold
(V_RESET) per the ordering information table. This register is
a non-volatile with no protection, therefore any writes to this
location can change the default value from that marked on
the package. If not changed with a non-volatile write, this
value will not change over normal operating and storage
conditions. However, ISL12029 has four (4) additional
selectable levels to fit the customers application. Levels are:
4.64V(default), 4.38V, 3.09V, 2.92V and 2.63V. The V_RESET
selection is via 3 bits (VTS2, VTS1 and VTS0) (see Table 6).
Care should be taken when changing the V_RESET select bits.
If the V_RESET voltage selected is higher than V_DD, then the
device will go into RESET and unless V_DD is increased, the
device will no longer be able to communicate using the I²C
bus.
14
FN6206.10
December 16, 2010