ISL12026_10 Datasheet, PDF (14/24 Pages) Intersil Corporation – Real Time Clock/Calendar with I2C Bus™ and EEPROM

ISL12026, ISL12026A
The ISL12026 device will switch from the V_BAT to V_DD mode
when one of the following conditions occurs:
- Condition 1:
V_DD > V_BAT + V_BATHYS
where V_BATHYS ≈ 50mV
- Condition 2:
V_DD > V_TRIP + V_TRIPHYS
where V_TRIPHYS ≈ 30mV
There are two discrete situations that are possible when
using Standard Mode: V_BAT < V_TRIP and V_BAT > V_TRIP.
These two power control situations are illustrated in Figures
9 and 10.
BATTERY BACKUP
V_DD
MODE
V_DD < V_BAT - V_BATHYS
• Battery Backup Mode (V_BAT) to Normal Mode (V_DD)
The device will switch from the V_BAT to V_DD mode when the
following condition occurs:
V_DD > V_BAT +V_BATHYS
The Legacy Mode power control conditions are illustrated in
Figure 11.
V_BAT
V_DD
Off
VOLTAGE
ON
In
V_TRIP
V_BAT
2.2V
1.8V
V_BAT - V_BATHYS
V_BAT + V_BATHYS
FIGURE 9. BATTERY SWITCHOVER WHEN V_BAT < V_TRIP
V_DD
V_BAT
V_TRIP
V_TRIP
BATTERY BACKUP
MODE
3.0V
2.2V
V_TRIP + V_TRIPHYS
FIGURE 10. BATTERY SWITCHOVER WHEN V_BAT > V_TRIP
OPTION 2 -LEGACY POWER CONTROL MODE
(ISL12026 DEFAULT)
The Legacy Mode follows conditions set in X1226 products.
In this mode, switching from V_DD to V_BAT is simply done by
comparing the voltages and the device operates from
whichever is the higher voltage. Care should be taken when
changing from Normal to Legacy Mode. If the V_BAT voltage is
higher than V_DD, then the device will enter battery back up
and unless the battery is disconnected or the voltage
decreases, the device will no longer operate from V_DD.
To select the Option 2, BSW bit in the Power Register must
be set to “BSW = 1”
• Normal Mode (V_DD) to Battery Backup Mode (V_BAT)
To transition from the V_DD to V_BAT mode, the following
conditions must be met:
FIGURE 11. BATTERY SWITCHOVER IN LEGACY MODE
Serial Communication
The device supports the I²C protocol.
Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions (see Figure 12).
Start Condition
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met (see Figure 13).
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
condition can only be issued after the transmitting device
has released the bus (see Figure 13).
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting 8 bits.
During the ninth clock cycle, the receiver will pull the SDA
line LOW to acknowledge that it received the 8 bits of data
(see Figure 14).
The device will respond with an acknowledge after
recognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave Address
Byte. If a write operation is selected, the device will respond
with an acknowledge after the receipt of each subsequent
8-bit word. The device will not acknowledge if the slave
address byte is incorrect.
14
FN8231.9
November 30, 2010