ICL7134 Datasheet, PDF (14/16 Pages) Intersil Corporation – 14-Bit Multiplying Microprocessor-Compatible D/A Converter

ICL7134
FIGURE 14. R650X AND MC680X FAMILIES’ INTERFACE TO
ICL7134
FIGURE 15. AVOIDING DIGITAL FEEDTHROUGH IN AN 8048
TO ICL7134 INTERFACE
FIGURE 16. ICL7134 TO 8048/80/85 INTERFACE WITH LOW FEEDTHROUGH
Digital Feedthrough
an MC6820 (R6520) PIA.
All of the direct interfaces shown above can suffer from a
capacitive coupling problem. The 14 data pins, and 4 control
pins, all tied to active lines on a microprocessor bus, and in
close proximity to the sensitive DAC circuitry, can couple
pseudo-random spikes into the analog output. Careful board
layout and shielding can minimize the problems (see PC
layout), and clearly wire-wrap type sockets should never be
used. Nevertheless, the inherent capacitance of the package
alone can lead to unacceptable digital feedthrough in many
cases. The only solution is to keep the digital input lines as
inactive as possible. One easy way to do this is to use the
peripheral interface circuitry available with all the systems
previously discussed. These generally allow only 8 bits to be
updated at any one time, but a little ingenuity will avoid diffi-
culties with DAC steps that would result from partial updates.
The problem can be solved for the 8048 family by tying the
14 port lines to the data input lines, with CS, A₀ and A₁ held
low, and using only the WR line to enter the data into the
DAC (as shown in Figure 15). WR is well separated from the
analog lines on the ICL7134, and is usually not a very active
line in 8048 systems. Additional “protection” can be achieved
by gating the processor WR line with another port line. The
same type of technique can be employed in the 8080/85
systems by using an 8255 PIA (peripheral Interface adaptor)
(Figure 16) and in the MC680X and R650X systems by using
Successive Approximation A/D Converters
Figure 17 shows an ICL7134B-based circuit for a bipolar
input high speed A/D converter, using two AM25LO3s to
form a 14-bit successive approximation register. The
comparator is a two-stage circuit with and HA2605 front-end
amplifier, used to reduce setting time problems at the
summing node (see A020). Careful offset-nulling of this
amplifier is needed, and if wide temperature range operation
is desired, and auto-null circuit using an ICL7650 is probably
advisable (see A053). The clock, using two Schmitt trigger
TTL gates, runs at a slower rate for the first 8 bits, where
setting-time is most critical, than for the last 6 bits. The short-
cycle line is shown tied to the 15th bit; if fewer bits are
required, it can be moved up accordingly. The circuit will
free-run if the HOLD/RUN input is held low, but will stop after
completing a conversion if the pin is high at that time. A low-
going pulse will restart it. The STATUS output indicates
when the device is operating, and the falling edge indicates
the availability of new data. A unipolar version may be con-
structed by tying the MSB (D₁₃) on an ICL7134U to pin 14
on the first AM25L03, deleting the reference inversion
amplifier A₄, and tying V_RFM and V_RFL.
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