ICL7134 Datasheet, PDF (12/16 Pages) Intersil Corporation – 14-Bit Multiplying Microprocessor-Compatible D/A Converter

ICL7134
FIGURE 10. BIPOLAR (2’S COMPLEMENT), FOUR-QUADRANT MULTIPLYING CIRCUIT
Offset Adjustment
1. Connect all data inputs and WR, CS, A₀ and A₁ to
DGND.
2. Adjust the offset zero-adjust trim-pot of the operational
amplifier A₂, if used, for a maximum of 0V ±50µV at
AGND_S .
3. Set data to 000000....00. Adjust the offset zero-adjust
trim-pot of any output op-amp A₁, for a maximum of 0V
±50µV at V_OUT.
4. Connect D₁₃ (MSB) data input to V+.
5. Adjust the offset zero-adjust trim-pot of op-amp A₃ for a
maximum of 0V ±50µV at the R_INV terminal (pin 19).
Gain Adjustment (Optional)
1. Connect WR, CS, A₀ and A₁ to DGND.
2. Connect D₀, D₁ ... D₁₂ to V+, D₁₃ (MSB) to DGND.
3. Monitor V_OUT for a -V_REF (1 - 1/2¹³) reading.
4. To increase V_OUT, connect a series resistor of 10Ω or
less between the A₁ output and the R_FB terminal (pin 21).
5 To decrease V_OUT , connect a series resistor of 5Ω or
less between the reference voltage and the V_RFL termi-
nal (pin 18).
Processor Interfacing
The ease of interfacing to a processor can be seen from
Figure 11, which shows the ICL7134 connected to an 8035
or any other processor such as an 8049. The data bus feeds
into both register inputs; three port lines, in combination with
the WR line, control the byte-wide loading into these
registers and then the DAC register. A complete DAC set-up
requies 4 write instructions to the port, to set up the address
and CS lines, and 3 external data transfers, one a dummy
for the final transfer to the DAC register.
A similar arrangement can be used with an 8080A, 8228,
and 8224 chip set. Figure 12 shows the circuit, which can be
arranged as a memory-mapped interface (using MEMW) or
as an I/O-mapped interface (using I/O WRITE). See A020
and R005 for discussions of the relative merits of memory-
mapped versus I/O-mapped interfacing, as well as some
other ideas on interfacing with 8080 processors. The 8085
processor has a very similar interface, except that the con-
trol lines available are slightly different, as shown in Figure
13. The decoding of the IO/M line, which controls memory-
mapped or I/O-mapped operation, is arbitrary, and can be
omitted if not necessary. Neither the MC680X nor R650X
processor families offer specific I/O operations. Figure 14
shows a suitable interface to either of these systems, using a
direct connection. Several other decoding options can be
used, depending on the other control signals generated in
the system. Note that the R650X family does not require
VMA to be decoded with the address lines.
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