ISL6218_14 Datasheet, PDF (13/19 Pages) Intersil Corporation – Precision Single-Phase Buck PWM Controller for Intel Mobile Voltage Positioning IMVP-IV and IMVP-IV+

ISL6218
R_ISEN
=
I_OC
⋅
r_(DSON)
M
I_OCSET −
⋅ 0.2175
2μA
− 130
(EQ. 3)
In Equation 3, M represents the number of Low-Side
MOSFETs. Using the examples above (I_OC = 40A,
I_OCSET = 15µA) and substituting the values M = 2,
r_DS(ON) = 4.5mΩ, R_ISEN is calculated to be 1370Ω.
Step 3: Thermal Compensation for r_DS(ON) (if desired)
If PTCs are used for thermal compensation, then R_ISEN is
found using the room temperature value of r_DS(ON). If
standard resistors are used for RISEN, then the “HOT” value
of r_DS(ON) should be used for this calculation.
MOSFET r_DS(ON) sensing provides advantages in cost,
efficiency, and board area. However, if more precise current
feedback is desired, a discrete Precision Current Sense
Resistor R_POWER may be inserted between the SOURCE of
each channel’s lower MOSFET and ground. The small R_ISEN
resistor, as previously described, is then replaced with a
standard 1% resistor and connected from the ISEN pin of the
ISL6218 controller to the SOURCE of the lower MOSFET.
BATTERY FEED-FORWARD COMPENSATION - VBAT
As shown in Figure 8, the ISL6218 incorporates Battery
Voltage Feed-Forward Compensation. This compensation
provides a constant Pulse Width Modulator Gain independent
of battery voltage. An understanding of this gain is required for
proper loop compensation. The Battery Voltage is connected
directly to the ISL6218 by the VBAT pin, and the gain of the
system ramp modulator is a constant 6.0.
FAULT PROTECTION
The ISL6218 protects the CPU from damaging stress levels.
The overcurrent trip point is integral in preventing output
shorts of varying degrees from causing current spikes that
would damage a CPU. The output overvoltage and
undervoltage detection features insure a safe window of
operation for the CPU.
OUTPUT VOLTAGE MONITORING
VSEN is connected to the local CORE Output Voltage and is
used for PGOOD, undervoltage and overvoltage sensing
only. (Refer to the “Block Diagram” on page 7).
The VSEN voltage is compared with two voltage levels that
indicate an overvoltage or undervoltage condition of the
output. Violating either of these conditions results in the
PGOOD pin toggling low to indicate a problem with the
output voltage.
RST
IPGT
START
t
S SET Q
ISL6218
3.3V
START
Q
1.2k
R _CLR
PGOOD
3.3V
ISL6225
10k
3.3V
PGOOD _VCCP
10k
t
~100ns
PGOOD
VCCP_MC
3ms TO 12ms
CPU-UP = UV AND OV
CLK_ENABLE
IMVP4_PWRGD
FIGURE 9. INTERNAL PGOOD CIRCUITRY FOR THE ISL6218
CORE VOLTAGE REGULATOR
PGOOD
As previously described, the ISL6218 PGOOD pin operates
as both an input and an output. During start-up, the PGOOD
pin operates as an input. Refer to Figure 9.
As per the IMVP-IV^™ specification, once the ISL6218 CORE
regulator regulates to the “Boot” voltage, it waits for the
PGOOD logic HIGH signals from the Vccp and Vcc_mch
regulators. The Intersil ISL6225 is a perfect choice for these
two supplies as it is a dual regulator and has independent
PGOOD functions for each supply. Once these two supplies
are within regulation, PGOOD_Vccp and PGOOD_{Vcc_mch} will
be high impedance, and will allow the PGOOD of the
ISL6218 to sink approximately 2.6mA to ground through the
internal MOSFET, shown in Figure 9. The ISL6218 detects
this current and starts an internal PGOOD timer.
The current sourced into the PGOOD pin is critical for proper
start-up operation. The pullup resistor, R_pull-up is sized to
give a minimum of 2.6mA of current sourced into the
PGOOD pin from 3.3V supply.
As given in the “Electrical Specifications” table on page 4,
the PGOOD MOSFET r_DS(ON) is given as 82Ω maximum. If
a 3.3V source is used as the Pull-up, then the Pull-up
resistor is given Equation 4:
( ) ^{( )} RPullup
=
VSOURCE
2.6mA
− rDSON max
3.3 − 0.05 3.3
=
2.6mA
− 82 = 1.2kΩ
(EQ. 4)
where V_SOURCE is the supply minus 5% for tolerance. This
will insure that the required PGOOD current will be sourced
into the PGOOD pin for worst case conditions of low supply
and largest MOSFET r_DS(ON).
Once the proper level of PGOOD current is detected, the
ISL6218 then captures the VID and regulates to this value.
The PGOOD timer is a function of the internal clock and
switching frequency. The internal PGOOD delay can be
calculated in Equation 5:
PGOOD Timer Delay = 3072 / f_SW
(EQ. 5)
13
FN9101.6
August 6, 2007