ISL6218_14 Datasheet, PDF (10/19 Pages) Intersil Corporation – Precision Single-Phase Buck PWM Controller for Intel Mobile Voltage Positioning IMVP-IV and IMVP-IV+

ISL6218
TABLE 1. INTEL IMPV-IV VID CODES (Continued)
VID5 VID4 VID3 VID2 VID1 VID0
VDAC
0
1
0
1
0
0
1.388
0
1
0
1
0
1
1.372
0
1
0
1
1
0
1.356
0
1
0
1
1
1
1.340
0
1
1
0
0
0
1.324
0
1
1
0
0
1
1.308
0
1
1
0
1
0
1.292
0
1
1
0
1
1
1.276
0
1
1
1
0
0
1.260
0
1
1
1
0
1
1.244
0
1
1
1
1
0
1.228
0
1
1
1
1
1
1.212
1
0
0
0
0
0
1.196
1
0
0
0
0
1
1.180
1
0
0
0
1
0
1.164
1
0
0
0
1
1
1.148
1
0
0
1
0
0
1.132
1
0
0
1
0
1
1.116
1
0
0
1
1
0
1.100
1
0
0
1
1
1
1.084
1
0
1
0
0
0
1.068
1
0
1
0
0
1
1.052
1
0
1
0
1
0
1.036
1
0
1
0
1
1
1.020
1
0
1
1
0
0
1.004
1
0
1
1
0
1
0.988
1
0
1
1
1
0
0.972
1
0
1
1
1
1
0.956
1
1
0
0
0
0
0.940
1
1
0
0
0
1
0.924
1
1
0
0
1
0
0.908
1
1
0
0
1
1
0.892
1
1
0
1
0
0
0.876
1
1
0
1
0
1
0.860
1
1
0
1
1
0
0.844
1
1
0
1
1
1
0.828
1
1
1
0
0
0
0.812
1
1
1
0
0
1
0.796
1
1
1
0
1
0
0.780
1
1
1
0
1
1
0.764
TABLE 1. INTEL IMPV-IV VID CODES (Continued)
VID5 VID4 VID3 VID2 VID1 VID0
VDAC
1
1
1
1
0
0
0.748
1
1
1
1
0
1
0.732
1
1
1
1
1
0
0.716
1
1
1
1
1
1
0.700
Active, Deep Sleep and Deeper Sleep Modes
The ISL6218 Single-Phase Controller is designed to control
the CORE output voltage as per the IMVP-IV^™ specifications
for Active, Deep Sleep, and Deeper Sleep Modes of
Operation.
After initial start-up, a logic high signal on DSEN and a logic
low signal on DRSEN signals the ISL6218 to operate in
Active mode (refer to Table 2). This mode will recognize VID
code changes and regulate the output voltage to these
command voltages.
A logic low signal present on STPCPU (pin DSEN), with a
logic low signal on DPRSLPVR (pin DRSEN) signals the
ISL6218 to reduce the CORE output voltage to the Deep
Sleep level, the voltage on the DSV pin.
A logic high on DPRSLPVR (pin DRSEN), with a logic low
signal on STPCPU (pin DSEN), signals the ISL6218
controller to further reduce the CORE output voltage to the
Deeper Sleep level, which is the voltage on the DRSV pin.
Deep Sleep and Deeper Sleep voltage levels are
programmable and are explained in “STV, DSV and DRSV”
on page 12.
TABLE 2. OUTPUT VOLTAGE AS A FUNCTION OF DSEN
AND DRSEN LOGIC STATES
DSEN -
STP_CPU
DRSEN -
DPRSLPVR
MODE OF
OPERATION
OUTPUT
VOLTAGE
1
0
Active
VID
0
0
Deep Sleep
DSV
0
1
Deeper Sleep
DRSV
1
1
Deeper Sleep
DRSV
10
FN9101.6
August 6, 2007