X9410_06 Datasheet, PDF (12/21 Pages) Intersil Corporation – Dual Digitally Controlled Potentiometer

X9410
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
V_CC x 0.1 to V_CC x 0.9
10ns
Input and output timing level V_CC x 0.5
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) t_PUR and t_PUW are the delays required from the time the
third (last) power supply (V_CC, V+ or V-) is stable until
the specific instruction can be issued. These parameters
are periodically sampled and not 100% tested.
Test Circuit #3 SPICE Macro Model
R_TOTAL
R_H
C_L
R_L
C_H
C_W
10pF
10pF
25pF
R_W
AC TIMING
Symbol
f_SCK
t_CYC
t_WH
t_WL
t_LEAD
t_LAG
t_SU
t_H
t_RI
t_FI
t_DIS
t_V
t_HO
t_RO
t_FO
t_HOLD
t_HSU
t_HH
t_HZ
t_LZ
T_I
t_CS
t_WPASU
t_WPAH
Parameter
SSI/SPI clock frequency
SSI/SPI clock cycle time
SSI/SPI clock high time
SSI/SPI clock low time
Lead time
Lag time
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable time
SO output valid time
SO output hold time
SO output rise time
SO output fall time
HOLD time
HOLD setup time
HOLD hold time
HOLD low to output in High Z
HOLD high to output in Low Z
Noise suppression time constant at SI, SCK, HOLD and CS inputs
CS deselect time
WP, A0 and A1 setup time
WP, A0 and A1 hold time
Min.
500
200
200
250
250
50
50
0
0
400
100
100
2
0
0
Max.
2.0
2
2
500
100
50
50
100
100
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
12
FN8193.2
October 12, 2006