X9258_13 Datasheet, PDF (12/19 Pages) Intersil Corporation – Low Noise/Low Power/2-Wire Bus/256 Taps

X9258
DC Operating Characteristics Over recommended operating conditions, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 12)
MAX
TYP (Note 12) UNIT
I_CC1
V_CC Supply Current (Nonvolatile
Write)
f_SCL = 400kHz, SDA = Open,
Other Inputs = V_SS
1
mA
I_CC2
V_CC Supply Current (Move Wiper, f_SCL = 400kHz, SDA = Open,
Write, Read)
Other Inputs = V_SS
100
µA
I_SB
V_CC Current (Standby)
SCL = SDA = V_CC, Addr. = V_SS
5
µA
I_LI
Input Leakage Current
V_IN = V_SS to V_CC
10
µA
I_LO
Output Leakage Current
V_OUT = V_SS to V_CC
10
µA
V_IH
Input HIGH Voltage
V_CC x 0.7
V_CC + 0.1
V
V_IL
Input LOW Voltage
-0.5
V_CC x 0.3
V
V_OL Output LOW Voltage
I_OL = 3mA
0.4
V
NOTES:
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
13. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
14. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is
a measure of the error in step size.
15. MI = R_TO_T/255 or (V_H/R_H—V_L/R_L)/255, single potentiometer.
16. Max = all four arrays cascaded together; typical = individual array resolutions.
Endurance and Data Retention
PARAMETER
Minimum Endurance
Data Retention
MIN
(Note 12)
100,000
100
UNIT
Data changes per bit per register
years
Capacitance
SYMBOL
PARAMETER
C_I/O (Note 17) Input/Output Capacitance (SDA)
C_IN (Note 17) Input Capacitance (A0, A1, A2, A3, and SCL)
TEST CONDITIONS
V_I/O = 0V
V_IN = 0V
MAX
(Note 12)
8
6
UNIT
pF
pF
Power-Up Timing
SYMBOL
PARAMETER
MIN
(Note 12)
MAX
(Note 12)
UNIT
t_PUR (Note 18) Power-up to Initiation of Read Operation
1
ms
t_PUW (Note 18) Power-up to Initiation of Write Operation
5
ms
t_R V_CC (Note 19) V_CC Power-up Ramp
0.2
50
V/ms
NOTES:
17. This parameter is periodically sampled and not 100% tested.
18. t_PUR and t_PUW are the delays required from the time the third (last) power supply (V_CC, V+ or V-) is stable until the specific instruction can be
issued. These parameters are periodically sampled and not 100% tested.
19. Sample tested only.
12
FN8168.6
December 15, 2011