X9221A_14 Datasheet, PDF (12/15 Pages) Intersil Corporation – Dual Digitally Controlled Potentiometer

X9221A
A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated)
Symbol
f_SCL
t_LOW
t_HIGH
t_R
t_F
T_i
t_SU:STA
t_HD:STA
t_SU:DAT
t_HD:DAT
t_AA
t_DH
t_SU:STO
t_BUF
t_WR
t_STPWV
t_CLWV
Parameter
SCL clock frequency
Clock LOW period
Clock HIGH period
SCL and SDA rise time
SCL and SDA fall time
Noise suppression time constant (glitch filter)
Start condition setup time (for a repeated start condition)
Start condition hold time
Data in setup time
Data in hold time
SCL LOW to SDA data out valid
Data out hold time
Stop condition setup time
Bus free time prior to new transmission
Write cycle time (nonvolatile write operation)
Wiper response time from stop generation
Wiper response from SCL LOW
Limits
Min. Max.
0
100
4700
4000
1000
300
100
4700
4000
250
0
300 3500
300
4700
4700
10
1000
500
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
µs
TIMING DIAGRAMS
Figure 10. Input Bus Timing
Reference
Figure
10
10
10
10
10
10
10 & 12
10 & 12
10
10
11
11
10 & 12
10
13
13
6
SCL
SDA
(Data in)
t_SU:STA
t_HIGH
t_LOW
t_HD:STA t_HD:DAT
t_F
t_SU:DAT
Figure 11. Output Bus Timing
t_R
t_SU:STO
t_BUF
SCL
SDA
t_AA
SDA_OUT (ACK)
t_DH
SDA_OUT
SDA_OUT
12
FN8163.2
August 30, 2006