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X9221A_14 Datasheet, PDF (10/15 Pages) Intersil Corporation – Dual Digitally Controlled Potentiometer
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X9221A
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
Min. Typ. Max. Unit
Test Conditions
lCC
Supply Current (Active)
3
mA fSCL = 100kHz, SDA = Open, Other Inputs = VSS
ISB
VCC Current (Standby)
200
500
µA SCL = SDA = VCC, Addr. = VSS
ILI
Input Leakage Current
10
µA VIN = VSS to VCC
ILO
Output Leakage Current
10
µA VOUT = VSS to VCC
VIH
Input HIGH Voltage
2
VCC + 1 V
VIL
Input LOW Voltage
-1
0.8
V
VOL Output LOW Voltage
0.4
V IOL = 3mA
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as
a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (VH/RH–VL/RL)/63, single pot
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
years
CAPACITANCE
Symbol
CI/O(5)
CIN(5)
Parameter
Input/output capacitance (SDA)
Input capacitance (A0, A1, A2, A3 and SCL)
Max.
8
6
Unit
pF
pF
Test Conditions
VI/O = 0V
VIN = 0V
POWER-UP TIMING
Symbol
tPUR(6)
tPUW(6)
tRVCC
Parameter
Power-up to initiation of read operation
Power-up to initiation of write operation
VCC Power-up ramp rate
Min.
0.2
Max.
1
5
50
Unit
ms
ms
V/ms
Notes: (5) This parameter is periodically sampled and not 100% tested.
(6) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are
periodically sampled and not 100% tested.
Power Up Requirements (Power up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First VCC, then the potentiometer pins. It is suggested that VCC
reach 90% of its final value before power is applied to the potentiometer pins. The VCC ramp rate specification should
be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible. Also, VCC should not
reverse polarity by more than 0.5V.
10
FN8163.2
August 30, 2006
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