ISL6753 Datasheet, PDF (12/15 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller

ISL6753
R6 = 499Ω
Solve for the current sense resistor, R_CS, using EQ. 18.
R_CS = 15.1Ω.
Determine the amount of voltage, Ve, that must be added to
the current feedback signal using EQ. 15.
Ve = 153mV
Next, determine the effect of the magnetizing current from
EQ. 20.
∆V_CS = 91mV
Using EQ. 23, solve for the summing resistor, R9, from
CTBUF to CS.
R9 = 30.1kΩ
Determine the new value of R_CS, R’_CS, using EQ. 24.
R’_CS = 15.4Ω
The above discussion determines the minimum external
ramp that is required. Additional slope compensation may be
considered for design margin.
f the application requires deadtime less than about 500nS,
the CTBUF signal may not perform adequately for slope
compensation. CTBUF lags the CT sawtooth waveform by
300-400nS. This behavior results in a non-zero value of
CTBUF when the next half-cycle begins when the deadtime
is short.
Under these situations, slope compensation may be added
by externally buffering the CT signal as shown below.
1
VREF 16
2
15
3
ISL6753
14
4
13
5 CT
12
6
11
R9
7
10
8 CS
9
R6
Using CT to provide slope compensation instead of CTBUF
requires the same calculations, except that EQs. 21 and 22
require modification. EQ. 21 becomes:
V_e – ∆V_CS
=
-²----^D------^â‹---^R-----⁶---
R6 + R9
V
(EQ. 25)
and EQ. 22 becomes:
R9 = -⁽--²----^D------–----^V----^e-----+-----^∆----^V----^C----^S----⁾----^â‹---^R----⁶--
Ω
V_e – ∆V_CS
(EQ. 26)
The buffer transistor used to create the external ramp from
CT should have a sufficiently high gain so as to minimize the
required base current. Whatever base current is required
reduces the charging current into CT and will reduce the
oscillator frequency.
ZVS Full-Bridge Operation
The ISL6753 is a full-bridge zero-voltage switching (ZVS)
PWM controller that behaves much like a traditional hard-
switched topology controller. Rather than drive the diagonal
bridge switches simultaneously, the upper switches (OUTUL,
OUTUR) are driven at a fixed 50% duty cycle and the lower
switches (OUTLL, OUTLR) are pulse width modulated on
the trailing edge.
CT
DEADTIME
OUTLL
OUTLR
PWM
PWM
PWM
PWM
OUTUR
RESONANT
DELAY
OUTUL
RESDEL
WINDOW
FIGURE 9. BRIDGE DRIVE SIGNAL TIMING
R_CS
C4
CT
FIGURE 8. ADDING SLOPE COMPENSATION USING CT
12
FN9182.1
March 10, 2005