ISL6527 Datasheet, PDF (12/16 Pages) Intersil Corporation – Single Synchronous Buck Pulse-Width Modulation PWM Controller

ISL6527, ISL6527A
approximate response time interval for application and
removal of a transient load:
t_RISE =
L x I_TRAN
V_IN - V_OUT
(EQ. 14)
t_FALL =
L x I_TRAN
V_OUT
(EQ. 15)
where: I_TRAN is the transient load current step, t_RISE is the
response time to the application of load, and t_FALL is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both Equations 14 and 15 at the
minimum and maximum output levels for the worst case
response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q₁ turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q₁ and the source of Q₂.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25x greater than the maximum input
voltage and a voltage rating of 1.5x is a conservative
guideline. The RMS current rating requirement for the input
capacitor of a buck regulator is approximately 1/2 the DC load
current.
The maximum RMS current required by the regulator may be
closely approximated through Equation 16:
I_RMSMAX =
V_{-----O----U----T--}
V_IN
×
⎛
⎜
⎝
I_O
U
TM
A
2
X
+
--¹----
12
×
⎛
⎜
⎝
-^V----^I--^N-----–----^V-----^O----^U----^T--
L × f_s
×
-^V---_V-^O---_I-^U-_N---^T--_{⎠⎟⎞}
2_⎞
⎟
⎠
(EQ. 16)
For a through-hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
MOSFET Selection/Considerations
The ISL6527, ISL6527A require two N-Channel power
MOSFETs. These should be selected based upon r_DS(ON),
gate supply requirements, and thermal management
requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed
between the two MOSFETs according to duty factor. The
switching losses seen when sourcing current will be different
from the switching losses seen when sinking current. When
sourcing current, the upper MOSFET realizes most of the
switching losses. The lower switch realizes most of the
switching losses when the converter is sinking current
(see Equations 17 and 18). These equations assume linear
voltage-current transitions and do not adequately model
power loss due the reverse-recovery of the upper and lower
MOSFET’s body diode. The gate-charge losses are
dissipated by the ISL6527, ISL6527A and don't heat the
MOSFETs. However, large gate-charge increases the
switching interval, t_SW which increases the MOSFET
switching losses. Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature
by calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may be
necessary depending upon MOSFET power, package type,
ambient temperature and air flow.
Losses while Sourcing current
P_UPPER
=
I
o²
×
r_D
S(
O
N
)
×
D
+
1_--
2
⋅
I
o
×
V_I
N
×
t_S
W
×
f_s
P_LOWER = Io² x r_DS(ON) x (1 - D)
(EQ. 17)
Losses while Sinking current
P_UPPER = Io² x r_DS(ON) x D
P_LOWER
=
Io²
×
r_DS(ON)
×
(1
–
D)
+
1_--
2
⋅
Io
×
V_IN
×
t_SW
×
f_s
(EQ. 18)
where: D is the duty cycle = V_OUT/V_IN, t_SW is the combined
switch ON- and OFF-time, and f_S is the switching frequency.
Given the reduced available gate bias voltage (5V), logic-level
or sub-logic-level transistors should be used for both
N-MOSFETs. Caution should be exercised with devices
exhibiting very low V_GS(ON) characteristics. The shoot-through
protection present aboard the ISL6527, ISL6527A may be
circumvented by these MOSFETs if they have large parasitic
impedances and/or capacitances that would inhibit the gate of
the MOSFET from being discharged below its threshold level
before the complementary MOSFET is turned on.
Bootstrap Component Selection
External bootstrap components, a diode and capacitor, are
required to provide sufficient gate enhancement to the upper
MOSFET. The internal MOSFET gate driver is supplied by the
external bootstrap circuitry as shown in Figure 7. The boot
capacitor, C_BOOT, develops a floating supply voltage
referenced to the PHASE pin. This supply is refreshed each
cycle, when D_BOOT conducts, to a voltage of CPVOUT less the
boot diode drop, V_D, plus the voltage rise across Q_LOWER.
12
FN9056.10
November 18, 2008