ISL6527 Datasheet, PDF (10/16 Pages) Intersil Corporation – Single Synchronous Buck Pulse-Width Modulation PWM Controller

ISL6527, ISL6527A
ISL6527, ISL6527A
+3.3V VIN
VCC
CVCC
CPVOUT
CBP
GND
CIN
D1
BOOT
UGATE
PHASE
LGATE
CBOOT
Q1
PHASE
LOUT
VOUT
Q2
COUT
COMP
FB
C2
C1
R2
R1
C3 R3
R4
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This function is dominated by a DC
Gain and the output filter (L_O and C_O), with a double pole
break frequency at F_LC and a zero at F_ESR. The DC Gain of
the modulator is simply the input voltage (V_IN) divided by the
peak-to-peak oscillator voltage ΔV_OSC.
Modulator Break Frequency Equations
F_LC=
--------------------¹---------------------
2π x L_O x C_O
(EQ. 5)
F_ESR=
---------------------¹---------------------
2π x ESR x C_O
(EQ. 6)
The compensation network consists of the error amplifier
(internal to the ISL6527, ISL6527A) and the impedance
networks Z_IN and Z_FB. The goal of the compensation
network is to provide a closed loop transfer function with the
highest 0dB crossing frequency (f_0dB) and adequate phase
margin. Phase margin is the difference between the closed
loop phase at f_0dB and 180°. Equations 7 through 10 relate
the compensation network’s poles, zeros and gain to the
components (R₁, R₂, R₃, C₁, C₂, and C₃) in Figure 5. Use
10
OSC
PWM
COMPARATOR
-
D VOSC
+
DRIVER
DRIVER
VIN
LO
VOUT
PHASE _CO
ZFB
VE/A
-
ZIN
+
ERROR ^REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C1
C2 R2
ZFB
VOUT
ZIN
C3 R3
R1
COMP
FB
-
+
ISL6527
REFERENCE
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
these guidelines for locating the poles and zeros of the
compensation network:
1. Pick gain (R₂/R₁) for desired converter bandwidth.
2. Place first zero below filter’s double pole (~75% F_LC).
3. Place second zero at filter’s double-pole.
4. Place first pole at the ESR zero.
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin; repeat if necessary.
Compensation Break Frequency Equations
F_Z1
=
----------------¹------------------
2π × R₂ × C₂
(EQ. 7)
F_P1
=
---------------------------¹-----------------------------
2π
x
R₂
x
⎛
⎜
⎝
C_{-C----1-1----+}x_{-----CC----2-2-⎠⎟⎞}
(EQ. 8)
F_Z2
=
---------------------------¹---------------------------
2π x (R₁ + R₃) x C₃
(EQ. 9)
F_P2 = -₂---_π------_x-----_R--¹--₃------_x-----_C----₃-
(EQ. 10)
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual modulator gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
compensation gain similar to the curve plotted. The open loop
FN9056.10
November 18, 2008