ISL6524 Datasheet, PDF (12/16 Pages) Intersil Corporation – VRM8.5 PWM and Triple Linear Power System Controller

Compensation Break Frequency Equations
F_Z1
=
-----------------¹------------------
2π × R2 × C1
F_P1
=
---------------------------¹---------------------------
2
π
×
R₂
×


C^-C----11^{-----+×-----CC-----22--}
F_Z2 = ₂----_π-----_×-----₍--_R-----₁-----+-¹----_R-----₃---₎----_×-----_C-----₃-
F_P2
=
-----------------¹------------------
2π × R3 × C3
Figure 12 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 12. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F_P2 with the capabilities
of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 12 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
100
F_Z1
F_Z2 F_P1 F_P2
OPEN LOOP
ERROR AMP GAIN
80
20 log



V----V-P----I-_–^-N----P--_{}
60
40
COMPENSATION
GAIN
20
0
-20
20
log


RR-----21--_
MODULATOR
-40
GAIN
F_LC F_ESR
CLOSED LOOP
GAIN
-60
10
100
1K
10K 100K 1M 10M
FREQUENCY (Hz)
FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than
45 degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converter requires an output capacitor
to filter the current ripple. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
12
PWM Output Capacitors
Modern microprocessors produce transient load rates
above 1A/ns. High frequency capacitors initially supply the
transient current and slow the load rate-of-change seen by
the bulk capacitors. The bulk filter capacitor values are
generally determined by the ESR (effective series
resistance) and voltage rating requirements rather than
actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage and
the initial voltage drop following a high slew-rate transient’s
edge. An aluminum electrolytic capacitor’s ESR value is
related to the case size with lower ESR available in larger
case sizes. However, the equivalent series inductance (ESL)
of these capacitors increases with case size and can reduce
the usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter. Work
with your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Linear Output Capacitors
The output capacitors for the linear regulators provide
dynamic load current. Thus capacitors C_OUT2, C_OUT3, and
C_OUT4 should be selected for transient load regulation.
PWM Output Inductor Selection
The PWM converter requires an output inductor. The output
inductor is selected to meet the output voltage ripple
requirements and sets the converter’s response time to a
load transient. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current. The ripple voltage and current are approximated by
the following equations:
∆I
=
V_{-----I--N-----–----}V_{-----O----U----T--}
F_S × L
×
-^V----^O----^U----^T--
V_IN
∆V_OUT = ∆I × ESR
Increasing the value of inductance reduces the ripple
current and voltage. However, large inductance values
increase the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6524 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
interval required to slew the inductor current from an initial
FN9015.3
April 18, 2005