ISL6524 Datasheet, PDF (11/16 Pages) Intersil Corporation – VRM8.5 PWM and Triple Linear Power System Controller

Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. The
power plane should support the input power and output
power nodes. Use copper filled polygons on the top and
bottom circuit layers for the PHASE node, but do not
unnecessarily oversize this particular island. Since the
PHASE node is subject to very high dV/dt voltages, the stray
capacitor formed between these island and the surrounding
circuitry will tend to couple switching noise. Use the
remaining printed circuit layers for small signal wiring. The
wiring traces from the control IC to the MOSFET gate and
source should be sized to carry 2A peak currents.
+5V_IN
L_IN
C_IN
+3.3V_IN
Q3
V_OUT2
C_OUT2
C_SS24,13
V_OUT3
+12V
C_VCC
VCC GND
C_OCSET
OCSET
DRIVE2
UGATE
R_OCSET
Q1
L_OUT
PHASE
V_OUT1
SS24
SS13
LGATE
Q2
ISL6524
C_OUT1
CR1
V_OUT4
C_OUT3
Q4
DRIVE3 DRIVE4
PGND
C_OUT4
Q5
+3.3V_IN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA/THROUGH-HOLE CONNECTION TO GROUND PLANE
FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
PWM1 Controller Feedback Compensation
The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration for a
voltage-mode controller requiring external compensation.
Figure 11 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V_OUT) is regulated to the Reference voltage level. The
reference voltage level is the DAC output voltage (DACOUT)
for the PWM. The error amplifier output (V_E/A) is compared with
the oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of V_IN at the PHASE node.
The PWM wave is smoothed by the output filter (L_O and C_O).
11
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This function is dominated by a DC
Gain, given by V_IN/V_OSC, and shaped by the output filter, with
a double pole break frequency at F_LC and a zero at F_ESR.
∆ V_OSC
OSC
PWM
COMP
-
+
V_IN
DRIVER
L_O
V_OUT
DRIVER
PHASE
C_O
V_E/A
Z_FB
-
+
ERROR
AMP
Z_IN
REFERENCE
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C2
C1 _R2
Z_FB
V_OUT
Z_IN
C3 R3
R1
COMP
FB
-
+
ISL6524
DACOUT
FIGURE 11. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
F_LC=
-------------------¹--------------------
2π × L_O × C_O
F_ESR=
--------------------¹---------------------
2π × ESR × C_O
The compensation network consists of the error amplifier
(internal to the ISL6524) and the impedance networks Z_IN and
Z_FB. The goal of the compensation network is to provide a
closed loop transfer function with high 0dB crossing frequency
(f_0dB) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f_0dB and 180^o.
The equations below relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 11. Use these guidelines for locating the poles
and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1^STZero Below Filter’s Double Pole (~75% F_LC)
3. Place 2^ND Zero at Filter’s Double Pole
4. Place 1^ST Pole at the ESR Zero
5. Place 2^ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
FN9015.3
April 18, 2005