ISL6445 Datasheet, PDF (12/15 Pages) Intersil Corporation – 1.4MHz Dual, 180 Out-of-Phase, Step-Down PWM Controller

ISL6445
There are two sets of critical components in a DC/DC
converter using the ISL6445. The switching power
components and the small signal components. The
switching power components are the most critical from a
layout point of view because they switch a large amount of
energy so they tend to generate a large amount of noise.
The critical small signal components are those connected to
sensitive nodes or those supplying critical bias currents. A
multi-layer printed circuit board is recommended.
Layout Considerations
1. The Input capacitors, Upper FET, Lower FET, Inductor
and Output capacitor should be placed first. Isolate these
power components on the topside of the board with their
ground terminals adjacent to one another. Place the input
high frequency decoupling ceramic capacitor very close
to the MOSFETs. Making the gate traces as short and
thick as possible will limit the parasitic inductance and
reduce the level of dv/dt seen at the gate of the lower
FETs when the upper FET turns on.
2. Use separate ground planes for power ground and small
signal ground. Connect the SGND and PGND together
close of the IC. Do not connect them together anywhere
else.
3. The loop formed by Input capacitor, the top FET and the
bottom FET must be kept as small as possible.
4. Insure the current paths from the input capacitor to the
MOSFET; to the output inductor and output capacitor are
as short as possible with maximum allowable trace
widths.
5. Place The PWM controller IC close to lower FET. The
LGATE connection should be short and wide. The IC can
be best placed over a quiet ground area. Avoid switching
ground loop current in this area.
6. Place VCC5 bypass capacitor very close to VCC5 pin of
the IC and connect its ground to the PGND plane.
7. Place the gate drive components BOOT diode and BOOT
capacitors together near controller IC.
8. The output capacitors should be placed as close to the
load as possible. Use short wide copper regions to
connect output capacitors to load to avoid inductance and
resistances.
9. Use copper filled polygons or wide but short trace to
connect junction of upper FET. Lower FET and output
inductor. Also keep the PHASE node connection to the IC
short. Do not unnecessary oversize the copper islands for
PHASE node. Since the phase nodes are subjected to
very high dv/dt voltages, the stray capacitor formed
between these islands and the surrounding circuitry will
tend to couple switching noise.
10. Route all high speed switching nodes away from the
control circuitry.
11. Create separate small analog ground plane near the IC.
Connect SGND pin to this plane. All small signal
grounding paths including feedback resistors, current
limit setting resistors, SDx pull-down resistors should be
connected to this SGND plane.
12. Ensure the feedback connection to output capacitor is
short and direct.
Component Selection Guidelines
MOSFET Considerations
The logic level MOSFETs are chosen for optimum efficiency
given the potentially wide input voltage range and output
power requirements. Two N-Channel MOSFETs are used in
each of the synchronous-rectified buck converters for the
PWM1 and PWM2 outputs. These MOSFETs should be
selected based upon r_DS(ON), gate supply requirements,
and thermal management considerations.
The power dissipation includes two loss components;
conduction loss and switching loss. These losses are
distributed between the upper and lower MOSFETs
according to duty cycle (see Equations 10 and 11). The
conduction losses are the main component of power
dissipation for the lower MOSFETs. Only the upper MOSFET
has significant switching losses, since the lower device turns
on and off into near zero voltage. Equations 10 and 11
assume linear voltage-current transitions and do not model
power loss due to the reverse-recovery of the lower
MOSFET’s body diode.
P_UPPER
=
(_---I_--O----²_---)_---(_--r_{---D----S----(--O----N----)---})_--(_---V_{----O----U----T----})
V_IN
+
(_---I_--O----)_---(_--V_{----I--N-----})_--(_--t_{--S----W------})_--(_--F_{----S----W------})
2
(EQ.
10)
P_LOWER
=
(_---I_--O----²_----)_--(_--r_{---D----S----(--O----N-----)--})_--(_---V_{----I--N-----–----}V_{-----O----U----T----})
V_IN
(EQ. 11)
A large gate-charge increases the switching time, t_SW,
which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications.
As the input voltage increases the power dissipation in the
internal +5V regulator increases. To ensure that the ISL6445
does not overheat choose the external MOSFETs based on
the total FET gate charge according the Figure 17. The plot
shows the maximum recommended gate charge for different
maximum ambient operating temperatures.
The power dissipation across the internal LDO comes from
the bias current for the chip as well as the current needed to
supply the internal gate drivers that drive the external
MOSFETs. The plot uses a recommended maximum
operating junction temperature of +125°C and calculates the
maximum gate charge based on the die temperature and the
maximum drive current that the internal LDO can supply.
12
FN9230.1
June 3, 2008