ISL6445 Datasheet, PDF (11/15 Pages) Intersil Corporation – 1.4MHz Dual, 180 Out-of-Phase, Step-Down PWM Controller

ISL6445
Over-Temperature Protection
The IC incorporates an over-temperature protection circuit
that shuts the IC down when a die temperature of +150°C
is reached. Normal operation resumes when the die
temperatures drops below +130°C through the initiation of
a full soft-start cycle.
Feedback Loop Compensation
To reduce the number of external components and to
simplify the process of determining compensation
components, both PWM controllers have internally
compensated error amplifiers. To make internal
compensation possible several design measures were
taken.
First, the ramp signal applied to the PWM comparator is
proportional to the input voltage provided via the VIN pin.
This keeps the modulator gain constant with variation in the
input voltage. Second, the load current proportional signal is
derived from the voltage drop across the lower MOSFET
during the PWM time interval and is subtracted from the
amplified error signal on the comparator input. This creates
an internal current control loop. The resistor connected to
the ISEN pin sets the gain in the current feedback loop.
Equation 6 estimates the required value of the current sense
resistor depending on the maximum operating load current
and the value of the MOSFET’s r_DS(ON).
R_CS
≥
-⁽--^I--^M-----^A----^X---⁾---⁽--^r---^D----^S----⁽--^O----^N----⁾---⁾
32 μ A
(EQ. 6)
Choosing R_CS to provide 32µA of current to the current
sample and hold circuitry is recommended but values down
to 2µA and up to 100µA can be used.
Due to the current loop feedback, the modulator has a single
pole response with -20dB slope at a frequency determined
by the load.
F_PO = ₂----_π-----_â‹---_R----¹-_O-----_â‹---_C-----_O--
(EQ. 7)
where R_O is load resistance and C_O is load capacitance. For
this type of modulator, a Type 2 compensation circuit is
usually sufficient.
Figure 16 shows a Type 2 amplifier and its response along
with the responses of the current mode modulator and the
converter. The Type 2 amplifier, in addition to the pole at
origin, has a zero-pole pair that causes a flat gain region at
frequencies in between the zero and the pole.
F_Z
=
--------------¹----------------
2π ⋅ R₂ ⋅ C₁
=
6kHz
(EQ. 8)
F_P = ₂----_π-----_â‹---_R--¹---₁----_â‹---_C-----₂- = 600kHz
(EQ. 9)
CONVERTER
EA
G_M = 17.5dB
MODULATOR
F_PO
C2
R2 ^C1
R1
TYPE 2 EA
G_EA = 18dB
F_Z
F_P
F_C
FIGURE 16. FEEDBACK LOOP COMPENSATION
The zero frequency, the amplifier high-frequency gain, and
the modulator gain are chosen to satisfy most typical
applications. The crossover frequency will appear at the
point where the modulator attenuation equals the amplifier
high frequency gain. The only task that the system designer
has to complete is to specify the output filter capacitors to
position the load main pole somewhere within one decade
lower than the amplifier zero frequency. With this type of
compensation plenty of phase margin is easily achieved due
to zero-pole pair phase ‘boost’.
Conditional stability may occur only when the main load pole
is positioned too much to the left side on the frequency axis
due to excessive output filter capacitance. In this case, the
ESR zero placed within the 1.2kHz to 30kHz range gives
some additional phase ‘boost’. Some phase boost can also
be achieved by connecting capacitor C_Z in parallel with the
upper resistor R₁ of the divider that sets the output voltage
value. Please refer to the “Output Inductor” and “Capacitor
Selection” on page 13 for further details.
Layout Guidelines
Careful attention to layout requirements is necessary for
successful implementation of a ISL6445 based DC/DC
converter. The ISL6445 switches at a very high frequency
and therefore the switching times are very short. At these
switching frequencies, even the shortest trace has
significant impedance. Also the peak gate drive current rises
significantly in extremely short time. Transition speed of the
current from one device to another causes voltage spikes
across the interconnecting impedances and parasitic circuit
elements. These voltage spikes can degrade efficiency,
generate EMI, increase device overvoltage stress and
ringing. Careful component selection and proper PC board
layout minimizes the magnitude of these voltage spikes.
11
FN9230.1
June 3, 2008