ISL22326_15 Datasheet, PDF (12/17 Pages) Intersil Corporation – Low Noise, Low Power, I2C™ Bus, 128 Taps

ISL22326
ADDRESS
8
7
6
5
4
3
2
1
0
TABLE 1. MEMORY MAP
NON-VOLATILE
VOLATILE
—
ACR
Reserved
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
Not Available
Not Available
Not Available
Not Available
Not Available
IVR1
IVR0
WR1
WR0
The non-volatile IVRi and volatile WRi registers are accessible
with the same address.
The Access Control Register (ACR) contains information
and control bits described in Table 2. The VOL bit at access
control register (ACR[7]) determines whether the access is
to wiper registers WRi or initial value registers IVRi.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
VOL
SHDN WIP
0
0
0
0
0
If VOL bit is 0, the non-volatile IVRi registers are accessible. If
VOL bit is 1, only the volatile WRi are accessible. Note, value
is written to IVRi register also is written to the corresponding
WRi. The default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shutdown mode.
This bit is logically ANDed with SHDN pin. When this bit is 0,
DCP is in Shutdown mode. Default value of SHDN bit is 1.
The WIP bit (ACR[5]) is read only bit. It indicates that
non-volatile write operation is in progress. It is impossible to
write to the IVRi, WRi or ACR while WIP bit is 1.
Shutdown Mode
The device can be put in Shutdown mode either by pulling the
SHDN pin to GND or setting the SHDN bit in the ACR register
to 0. The truth table for Shutdown mode is in Table 3.
SHDN pin
High
Low
High
Low
TABLE 3.
SHDN bit
1
1
0
0
Mode
Normal operation
Shutdown
Shutdown
Shutdown
I²C Serial Interface
The ISL22326 supports an I²C bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL22326
operates as a slave device in all applications.
All communication over the I²C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions
(see Figure 16). On power-up of the ISL22326, the SDA pin
is in the input mode.
All I²C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22326 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 16). A START condition is ignored during the
power-up of the device.
All I²C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 16). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 17).
The ISL22326 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22326 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
A valid Identification Byte contains 1010 as the four MSBs,
and the following three bits matching the logic values present
at pins A2, A1, and A0. The LSB is the Read/Write bit. Its
value is “1” for a Read operation, and “0” for a Write operation
(see Table 4).
TABLE 4. IDENTIFICATION BYTE FORMAT
Logic values at pins A2, A1, and A0 respectively
1
0
1
0
A2
A1
A0 R/W
(MSB)
(LSB)
12
FN6176.3
September 9, 2015