ICM7228 Datasheet, PDF (12/17 Pages) Intersil Corporation – 8-Digit, Microprocessor- Compatible, LED Display Decoder Driver

ICM7228
Detailed Description
System Interfacing and Data Entry Modes, ICM7228A
and ICM7228B
The ICM7228A/B devices are compatible with the architec-
tures of most microprocessor systems. Their fast switching
characteristics makes it possible to access them as a memory
mapped I/O device with no wait state necessary in most
microcontroller systems. All the ICM7228A/B inputs, including
MODE, feature a 250ns minimum setup and 0ns hold time
with a 200ns minimum WRITE pulse. Input logic levels are
TTL and CMOS compatible. Figure 9 shows a generic method
of driving the ICM7228A/B from a microprocessor bus. To the
microprocessor, each device appears to be 2 separate I/O
locations; the Control Register and the Display RAM. Selec-
tion between the two is accomplished by the MODE input
driven by address line A0. Input data is placed on the lD0 - lD7
lines. The WRITE input acts as both a device select and write
cycle timing pulse. See Figure 1 and Switching Specifications
Table for write cycle timing parameters.
The ICM7228A/B have three data entry modes: Control Reg-
ister update without RAM update, sequential 8-digit update
and single digit update. In all three modes a control word is
first written by pulsing the WRITE input while the MODE input
is high, thereby latching data into the Control Register. The
logic level of individual bits in the Control Register select Shut-
down, Decode/No Decode, Hex/Code B, RAM bank A/B and
Display RAM digit address as shown in Tables 1 and 2.
The ICM7228A/B Display RAM is divided into 2 banks, called
bank A and B. When using the Hexadecimal or code B display
modes, these RAM banks can be selected separately. This
allows two separate sets of display data to be stored and dis-
played alternately. Notice that the RAM bank selection is not
possible in No-Decode mode, this is because the display data
in the No-Decode mode has 8 bits, but in Decoded schemes
(Hex/Code B) is only 4 bits (lD0 - lD3 data). It should also be
mentioned that the decimal point is independent of selected
bank, a turned on decimal point will remain on for either bank.
Selection of the RAM banks is controlled by lD3 input. The lD3
logic level (during Control Register update) selects which bank
of the internal RAM to be written to and/or displayed.
Control Register Update without RAM Update
The Control Register can be updated without changing the
display data by a single pulse on the WRITE input, with MODE
high and DATA COMING low. If the display is being decoded
(Hex/Code B), then the value of lD3 determines which RAM
bank will be selected and displayed for all eight digits.
Sequential 8-Digit Update
The logic state of DATA COMING (lD7) is also latched during a
Control Register update. If the latched value of DATA COMING
(lD7) is high, the display becomes blanked and a sequential
8-digit update is initiated. Display data can now be written into
RAM with 8 successive WRITE pulses, starting with digit 1 and
ending with digit 8 (See Figure 2). After all 8 RAM locations
have been written to, the display turns on again and the new
data is displayed. Additional write pulses are ignored until a new
Control Register update is performed. All 8 digits are displayed
in the format (Hex/Code B or No Decode) specified by the con-
trol word that preceded the 8 digit update. If a decoding scheme
(Hex/Code B) is to be used, the value of lD3 during the control
word update determines which RAM bank will be written to.
Single Digit Update
In this mode each digit data in the display RAM can be updated
individually without changing the other display data. First, with
MODE input high, a control word is written to the Control Regis-
ter carrying the following information; DATA COMING (lD7) low,
the desired display format data on lD4 - lD6, the RAM bank
selected by lD3 (if decoding is selected) and the address of the
digit to be updated on data lines lD0 - lD2 (See Table 5). A sec-
ond write to the ICM7228A/B, this time with MODE input low,
transfers the data at the lD0 - lD7 inputs into the selected digit’s
RAM location. In single digit update mode, each individual
digit’s data can be specified independently for being displayed
in Decoded or No-Decode mode. For those digits which decod-
ing scheme (Hex/Code B) is selected, only one can be effective
at a time. Whenever a control word is written, the specified
decoding scheme will be applied to all those digits which
selected to be displayed in Decoded mode.
I/O OR
MEMORY
WRITE PULSE
A1-A15
DATA BUS D0-D7
DECODER
ENABLE
ADDRESS
DECODER
D0 - D7
DEVICE SELECT
AND
WRITE PULSE
A0
ID0
ID7 INTERSIL
ICM7228A/B
SEGMENTS
WRITE
DRIVE
MODE
DIGITS
DRIVE
LED DISPLAY
ADDRESS BUS A0 - A15
FIGURE 9. ICM7228A/B MICROPROCESSOR SYSTEM INTERFACING
9-28