ISL6531 Datasheet, PDF (11/17 Pages) Intersil Corporation – Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination

ISL6531
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.f
ISL6531
+5V V_IN
VCC
C_BP
GND
D1
C_IN
BOOT1
UGATE1
PHASE1
LGATE1
PGND1
COMP1
FB1
C_BOOT1
Q1
PHASE1
L_OUT1
V_DDQ
Q2
C_OUT1
C_2A
R_2A
C_1A
R_1A
R4
C_3A R_3A
SENSE1
+5V V_IN
BOOT2
UGATE2
PHASE2
LGATE2
PGND2
D2 ^VDDQ
C_BOOT2
Q3
PHASE2
L_OUT2
V_TT
Q4
C_OUT2
SENSE2
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
The switching components should be placed close to the
ISL6531 first. Minimize the length of the connections
between the input capacitors, C_IN, and the power switches
by placing them nearby. Position both the ceramic and bulk
input capacitors as close to the upper MOSFET drain as
possible. Position the output inductor and output capacitors
between the upper MOSFET and lower diode and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Position the bypass capacitor, C_BP, close to the
VCC pin with a via directly to the ground plane. Place the
PWM converter compensation components close to the FB
and COMP pins. The feedback resistors for both regulators
should also be located as close as possible to the relevant
FB pin with vias tied straight to the ground plane as required.
V_DDQ Feedback Compensation
This section discusses the feedback compensation of the
V_DDQ regulator. Figure 8 highlights the voltage-mode
control loop for a synchronous-rectified buck converter. The
output voltage (V_OUT) is regulated to the Reference voltage
level. The error amplifier (error amp) output (V_E/A) is
compared with the oscillator (OSC) triangular wave to
provide a pulse-width modulated (PWM) wave with an
amplitude of V_IN at the PHASE node. The PWM wave is
smoothed by the output filter (L_O and C_O).
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This function is dominated by a DC
gain and the output filter (L_O and C_O), with a double pole
break frequency at F_LC and a zero at F_ESR. The DC gain of
the modulator is simply the input voltage (V_IN) divided by the
peak-to-peak oscillator voltage ∆V_OSC.
OSC
PWM
DRIVER
COMPARATOR
DV_OSC
+-
DRIVER
V_IN
L_O
PHASE _CO
V_OUT
Z_FB
V_E/A
+-
Z_IN
ERROR ^REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C₁
C₂ R₂
Z_FB
V_OUT
Z_IN
C_{3 R3}
COMP
R₁
FB
-
+
ISL6531
REFERENCE
FIGURE 8. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
F_LC=
--------------------¹---------------------
2π x L_O x C_O
F_ESR=
---------------------¹---------------------
2π x ESR x C_O
11