ISL6531 Datasheet, PDF (10/17 Pages) Intersil Corporation – Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination

ISL6531
normal operating load range, find the R_OCSET resistor from
the equation above with:
1. The maximum r_DS(ON) at the highest junction
temperature.
2. The minimum I_OCSET from the specification table.
3. Determine I_PEAK for
I_P
EAK
>
I_OUT
(MAX)
+
(_---∆_----I_---)
2
,
where ∆I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled Output Inductor Selection.
A small ceramic capacitor should be placed in parallel with
R_OCSET to smooth the voltage across R_OCSET in the
presence of switching noise on the input voltage.
Current Sinking
The ISL6531 V_TT regulator incorporates a MOSFET shoot-
through protection method which allows the converter to sink
current as well as source current. Care should be exercised
when designing a converter with the ISL6531 when it is
known that the converter may sink current.
When the converter is sinking current, it is behaving as a
boost converter that is regulating its input voltage. This
means that the converter is boosting current into the input
rail of the regulator. If there is nowhere for this current to go,
such as to other distributed loads on the rail or through a
voltage limiting protection device, the capacitance on this rail
will absorb the current. This situation will the allow voltage
level of the input rail to increase. If the voltage level of the rail
is boosted to a level that exceeds the maximum voltage
rating of any components attached to the input rail, then
those components may experience an irreversible failure or
experience stress that may shorten their lifespan. Ensuring
that there is a path for the current to flow other than the
capacitance on the rail will prevent this failure mode.
To insure that the current does not boost up the input rail
voltage of the V_TT regulator, it is recommended that the
input rail of the V_TT regulator be the output of the V_DDQ
regulator. The current being sunk by the V_TT regulator will
be fed into the V_DDQ rail and then drawn into the DDR
SDRAM memory module and back into the V_TT regulator.
Figure 6 shows the recommended configuration and the
resulting current loop.
+5V
ISL6531
UGATE1
PHASE1
LGATE1
UGATE2
PHASE2
LGATE2
V_DDQ
DDR
SDRAM
+
V_{TT RT}
-
V_REF
FIGURE 6. V_TT CURRENT SINKING LOOP
Application Guidelines
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
300kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device over-voltage stress. Careful component
layout and printed circuit board design minimizes the voltage
spikes in the converters.
As an example, consider the turn-off transition of the PWM
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower MOSFET. Any
parasitic inductance in the switched current path generates a
large voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide traces minimizes the magnitude of voltage
spikes.
There are two sets of critical components in a DC-DC
converter using the ISL6531. The switching components are
the most critical because they switch large amounts o
energy, and therefore tend to generate large amounts of
noise. Next are the small signal components which connect
to sensitive nodes or supply critical bypass current and
signal coupling.
A multi-layer printed circuit board is recommended. Figure 7
shows the connections of the critical components in the
converter. Note that capacitors C_IN and C_OUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections
with vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminals to the output inductor short. The power
plane should support the input power and output power
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