ISL5586 Datasheet, PDF (11/20 Pages) Intersil Corporation – Low Power Ringing SLIC for Home Gateways

ISL5586
I₁
POL
75kΩ
C_POL
I₂
FIGURE 7. REVERSAL TIMING CONTROL
Power Dissipation
The power dissipation equations for forward active operation
also apply to the reverse active mode.
Ringing
Overview
The Ringing mode (RNG, 100) provides linear amplification
to support a variety of ringing waveforms. A programmable
ring trip function provides loop supervision and auto
disconnect upon ring trip. The device is designed to operate
from the high battery during this mode.
Architecture
The SLIC provides linear amplification to the differential
signal applied to the ringing inputs (V_RSP, V_RSM). The
differential ringing gain of the device is 100V/V. The circuit
model for the ringing path is shown in Figure 8.
R
20
-
+
TIP
RING 20
+_-
R
R/8
+_- VBH
2
5:1
1.25R
R
1.25R
R
V_RSP
V_RSM
FIGURE 8. LINEAR RINGING MODEL
The voltage gain from the differential ringing input to the Tip
output is 50V/V. The resistor ratios provide a gain of 10 and
the current mirror provides a gain of 5. The voltage gain from
the differential input to the Ring output is -50V/V. The
equations for the Tip and Ring outputs during ringing are
provided below.
V_T= -^V----^B₂----^H-- + (50 × V_DIF )
(EQ. 29)
4-11
V_R= -^V----^B₂---^H---–(50 × V_DIF)
(EQ. 30)
When the differential input signal is zero, the Tip and Ring
amplifier outputs are centered at half battery. The device
provides auto centering for easy implementation of
sinusoidal ringing waveforms. Both AC and DC control of the
Tip and Ring outputs is available during ringing. This feature
allows for DC offsets as part of the ringing waveform.
Ringing Input Terminals
The differential terminals feature high input impedance
which allows the use of low value capacitors for AC coupling
the ring signal if necessary. The Ringing input is enabled
only during the ringing mode, therefore a free running
oscillator may be connected at all times.
When operating from a battery of -100V, each amplifier, Tip
and Ring, will swing a maximum of 95V_P-P. Hence, the
maximum differential signal swing between V_RSP and V_RSM
to achieve full scale ringing is approximately 1.9V_P-P.
Logic Control
Ringing patterns consist of silent and ringing intervals. The
ringing to silent pattern is called the ringing cadence. During
the silent portion of ringing, the device can be programmed
to any other operating mode. The most likely candidates are
low power standby or forward active. Depending on system
requirements, the low or high battery may be selected.
Loop supervision is provided with the ring trip detector. The ring
trip detector senses the change in loop current when the phone
is taken off hook. The loop detector full-wave rectifies the
ringing current, which is then filtered with external components
R_RT and C_RT. The resistor R_RT sets the trip threshold and the
capacitor C_RT sets the trip response time. Most applications will
require a trip response time less than 150ms.
Three very distinct actions occur when the device detects a
ring trip. First, the DET output is latched low. The latching
mechanism eliminates the need for software filtering of the
detector output. The latch is cleared when the operating
mode is changed externally. Second, the Ringing inputs are
disabled, removing the ring signal from the line. Third, the
device is internally forced to the forward active mode.
Power Dissipation
The power dissipation during ringing is dictated mostly by the
load driving requirements and the ringing waveform. The key to
valid power calculations is the correct definition of average and
RMS currents. The average current defines the high battery
supply current. The RMS current defines the load current.
The cadence provides a time averaging reduction in the
peak power. The total power dissipation consists of ringing
power, P_r, and the silent interval power, P_s.
P_RNG= P_r × -_t-_r----+^t--^r--_t--_s- + P_s × -_t--_r---^t_+-^s----_t--_s-
(EQ. 31)