ISL55033_15 Datasheet, PDF (11/13 Pages) Intersil Corporation – 400MHz Slew Rate Enhanced, Rail-to-Rail Output Gain Block

ISL55033
Application Information
General
The ISL55033 single supply, fixed gain, triple amplifier is
intended for use in a variety of video and other high speed
applications. The device features a ground-sensing PNP input
stage and a bipolar rail-to-rail output stage. The three amplifiers
have an internally fixed gain of 2 and share a single enable pin as
shown in Figure 32.
Ground Connections
For the best isolation performance and crosstalk rejection, all
GND pins must connect directly to the GND plane. In addition, the
electrically conductive thermal pad (EP) must also connect
directly to ground.
Power Considerations
Separate V+ power supply and GND pins for the input and output
stages are provided to maximize PSRR. Providing separate
power pins provides a way to prevent high speed transient
currents in the output stage from bleeding into the sensitive
amplifier input and gain stages. To maximize crosstalk isolation,
each power supply pin should have its own decoupling capacitors
connected as close to the pin as possible as shown in Figure 32
(0.1µF in parallel with 1nF recommended).
The ESD protection circuits use internal diodes from all pins to the
V+ and ground pins. In addition, a dV/dt-triggered clamp is
connected between the V+ and V- pins, as shown in Equivalent
Circuit 1 on page 2. The dV/dt triggered clamp imposes a
maximum supply turn-on slew rate of 1V/µs. Damaging currents
can flow for power supply slew rates in excess of 1V/µs, such as
during hot plugging. Under these conditions, additional methods
should be employed to ensure the maximum supply slew rate is
not exceeded.
Single Supply Input/Output Considerations
For best performance, the input signal voltage range should be
maintained between 0.1V to 2.1V. These input limits correspond
to an output voltage range of 0.2V to 4.2V and define the limits
of linear operation. Figure 4 shows the frequency response
versus the input DC voltage level. Figures 16 and 17 show the
differential gain-phase performance over the input range of 0V to
2.4V operating into a 150Ω load. The 0.1V to 2.1V input levels
corresponds to a 0.2V to 4.2V output levels, which define the
minimum and maximum range of output linear operation.
Composite video with sync requires care to ensure that the
negative sync tip voltage (typically -300mV) is properly
level-shifted up into the ISL55033 input linear operating region
of +0.1V to 2.1V. The high input impedance enables AC coupling
using low values of coupling capacitance with relatively high
input voltage divider resistances.
EN and Power-down States
The EN pin is active low. An internal pull-down resistor ensures
the device will be active with no connection to the EN pin. The
power-down state is established within approximately 25ns, if a
logic high (>2V) is placed on the EN pin. In the power-down state,
supply current is reduced significantly by shutting the three
amplifiers off. The output presents a relatively high impedance
(~2kΩ) to the output pin. Multiplexing several outputs together is
possible using the enable/disable function as long as the
application can tolerate the limited power-down output
impedance.
Limiting the Output Current
No output short-circuit current limit exists on these parts. All
applications need to limit the output current to less than 40mA.
Adequate thermal heat sinking of the parts is also required.
PC Board Layout
The AC performance of this circuit depends greatly on the care
taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components, such as chip resistors
and chip capacitors, is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid sharp
corners. Use rounded corners when possible. Vias in the signal
lines add inductance at high frequency and should be avoided.
PCB traces greater than 1" begin to exhibit transmission line
characteristics with signal rise/fall times of 1ns or less. High
frequency performance may be degraded for traces greater
than one inch, unless controlled impedance (50Ωor75Ωstrip
lines or microstrips are used.
• Match channel-to-channel analog I/O trace lengths and layout
symmetry. This will minimize propagation delay mismatches.
• Maximize use of AC decoupled PCB layers. All signal I/O lines
should be routed over continuous ground planes (i.e. no split
planes or PCB gaps under these lines). Avoid vias in the signal I/O
lines.
• Use proper value and location of termination resistors. Input
termination resistors should be as close to the input terminal as
possible and output termination resistors as close to the receiving
device as possible.
• When testing, use good quality connectors and cables, matching
cable types and keeping cable lengths to a minimum.
• A minimum of two, high frequency, power supply decoupling
capacitors (1000pF, 0.1µF), on each V+ pin, are recommended as
close to the devices as possible. Avoid vias between the capacitor
and the device because vias add unwanted inductance. Larger
capacitors (e.g., electrolytics) can be farther away. When vias are
required in a layout, they should be routed as far away from the
device as possible.
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FN6346.1
June 29, 2015